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Synthesizable Verilog

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AKSHAYNIMBAL

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Can anyone tell me how do is it feasible to do complex matrix operations in verilog which has to be synthesized? Or its better using DSP processor?


How do i handle real values in verilog which has to be synthesized?


Regards,
Akshay


Thank You
 

verilog data types are essentially arrays of bits. you have to pack the info you want in a way to has a meaning, typically using mantissa and exponent. there are lots of floating point libraries available.
 

Thank youThisIsNotSam.
Can you name few libraries to do so?? I'm using Xilinx Vertex 5 FPGA for the same.
It would be a great help if you direct me to something that has some very good resources for the same.

I even tried using Vivado HLS but still the verilog form of C gives an array of bits. But i wanted an array of numbers like [7:0]arr[0:3][0:3].

Thank you.
 

DSP vs FPGA for floating point is a valid case study, as some DSP's have hard IP FPU's and MMU support for DSP based applications.

For and FPGA using Verilog, you would be specifying the FPU's yourself (using coregen or other ip-cores normally) as well as any memory features (more ip-cores) and then writing a few FSM's to move data and control these FPU's.
 

AKSHAYNIMBAL said:
T
I even tried using Vivado HLS but still the verilog form of C gives an array of bits. But i wanted an array of numbers like [7:0]arr[0:3][0:3].

Thank you.
Click to expand...

There are no memories in the FPGA that have two indicies: arr[0:3][0:3], if you want to emulate a 2D array of bits then you have to index a regular memory bram_arr[0:15] like so:
Generic case:
bram_arr[4*y+x]

Your specific case of 4x4 (assuming x and y are declared as 2-bits):
bram_arr[{x,y}]
 

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