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help in understanding code (verilog)

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UltraGreen

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help in understanding code ( verilog )

Hello All, I am very new to System verilog and I do not understand the code below. i.e. after 1 bit hold and 128 bit Out has been declared as logic, what is CGlobal CGlobal(); means ?
Also after that, what does the assign statements do here. i.e. clkA is assigned to CGlobal.clkA
is it an array ? if it is then, how is the indexing happening here ?

Code:
.
.
logic                                   hold;
logic [127:0]                        Out;
CGlobal                              CGlobal();

assign CGlobal.clkA    = clkA    ; 
assign CGlobal.clkB    = clkB    ;
.
.



Similarly such notations are also there in other files inside port declaration -
Code:
.
.
.
input logic [11:0]   wr_xtern,
CGlobal.slave        CGlobal
 );

Thanks in advance
 

Re: help in understanding code ( verilog )

Look into "interface" and "modport".
 

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