shaiko
Advanced Member level 5
Hello,
My VHDL testbench has a simulated clock mux described as follows:
The above component is instantiated in my design and "clock_mux_out" is used to drive a synchronous process :
When I observe the waveform - it's twilight zone:
"some_registered_signal" isn't delayed by a clock cycle as I expected it to be - it's a direct copy of "some_signal" !
I go back to my code, omit the simulated clock mux - and drive the "clock_mux_out" signal directly by one of the input clocks:
The problem goes away.
What's going on ?
My VHDL testbench has a simulated clock mux described as follows:
Code:
entity simulated_clock_mux is
port
(
IN_CLOCK_0 : in std_logic ;
IN_CLOCK_1 : in std_logic ;
IN_CLOCK_2 : in std_logic ;
IN_CLOCK_3 : in std_logic ;
IN_SELECT : in std_logic_vector ( 1 downto 0 ) ;
OUT_CLOCK : out std_logic
) ;
end entity simulated_altclkctrl_video ;
architecture simulated_clock_mux of clock_mux is
signal clock_vector : std_logic_vector ( 3 downto 0 ) ;
begin
clock_vector <= IN_CLOCK_3 & IN_CLOCK_2 & IN_CLOCK_1 & IN_CLOCK_0 ;
OUT_CLOCK <= clock_vector ( to_integer ( unsigned ( IN_SELECT ) ) ) ;
end architecture simulated_clock_mux ;
The above component is instantiated in my design and "clock_mux_out" is used to drive a synchronous process :
Code:
simulated_clock_mux_inst : simulated_clock_mux
port map
(
IN_CLOCK_0 => simulated_clock_0 ,
IN_CLOCK_1 => simulated_clock_1 ,
IN_CLOCK_2 => simulated_clock_2 ,
IN_CLOCK_3 => simulated_clock_3 ,
IN_SELECT => clock_selector ,
OUT_CLOCK => clock_mux_out
) ;
process ( clock_mux_out , reset ) is
begin
if reset = '1' then
some_registered_signal <= '0' ;
elsif rising_edge ( clock_mux_out ) then
some_registered_signal <= some_signal ;
end if ;
end process ;
When I observe the waveform - it's twilight zone:
"some_registered_signal" isn't delayed by a clock cycle as I expected it to be - it's a direct copy of "some_signal" !
I go back to my code, omit the simulated clock mux - and drive the "clock_mux_out" signal directly by one of the input clocks:
Code:
--simulated_clock_mux_inst : simulated_clock_mux
--port map
--(
-- IN_CLOCK_0 => simulated_clock_0 ,
-- IN_CLOCK_1 => simulated_clock_1 ,
-- IN_CLOCK_2 => simulated_clock_2 ,
-- IN_CLOCK_3 => simulated_clock_3 ,
-- IN_SELECT => clock_selector ,
-- OUT_CLOCK => clock_mux_out
--) ;
clock_mux_out <= simulated_clock_0 ;
The problem goes away.
What's going on ?