Using data that read from memory increase fpga resources

hi,
when i make a comparison operation between 32 bit reg,lets say x>y both registers are not from the embedded memory the fpga resources that it require are much less(3 times) than if i will read y from embedded memory in the fpga(of course i put y in the memory in the previous cycles).

my question is how i can avoid this increase in resources? i understand that in the first case the synthesize tool know y reg value but at the second it doesn't,that is all the difference for me,i am sure there is any technique to avoid this increase in resources,after all the use of memory suppose to decrease not to increase the fpga resources(Luts).

this is the instantiation of the ram module without output register:
ram_dq u1(.Clock(clk),.ClockEn(clk_enable),.Reset(~reset),.WE(wr),.Address(addr_hu_rise),.Data(hu_rise_in),.Q(hu_rise));

hu_rise is the output that i make on it a comparison.

Hi,

It seems ... what you need is pipelinig.

Assuming your external bus width is 8 bits, then
* fetch byte1
* fetch byte2, compare byte1
* fetch byte3, compare byte2
* fetch byte4, compare byte3
* compare byte4 and combine it with the results of the 3 compares before.

Klaus

when i make a comparison operation between 32 bit reg,lets say x>y both registers are not from the embedded memory the fpga resources that it require are much less(3 times) than if i will read y from embedded memory in the fpga(of course i put y in the memory in the previous cycles).

Click to expand...

Your question is not clear to me.

There are two types of memories available in FPGAs, - BRAM and DRAM. Are you asking the difference in resource utilization when:
1> both regs belong to the same BRAM
2> both regs belong to same DRAM
3> one reg in BRAM and another in DRAM
4> both regs in different DRAMs

hi,
i use lattice MachXO2 device if u familiar with it.
the memory that i use is sysMEM EBR blocks.

i dont know what is it BRAM?

lets say i have that code:

if(pos>hu_rise)begin
hu<=1'b1;
end else begin
hu<=1'b0;
end

pos is 32 bit register that is change it's value every 64 microseconds(position from encoder if u know what is it)
i get the data from input pin and after i get all the data put it in reg pos,so pos save it's value for 64 microseconds.
pos is a regular register that i declare in my verilog code(reg[31:0] pos),so it's use the resources of the fpga(registers/Luts).

hu_rise is the output of dram memory that is embedded in that fpga and i instantiate it.

when previously i make my own memory from fpga resources:

reg[31:0] hu_rise[0:31]

it's took for me less resources when i make this comparison(code above) than if i use the embedded memory.
the only diffrence is that when i use embedded memory(DRAM) i put the values in it at run time.
when i build my own memory i guess the values are calculated during synthesize process.

I mainly work with Xilinx FPGAs, which have embedded memory in the form of :
BRAM- BlockRAM, and
DRAM- DistributedRAM

I am not at all familiar with lattice MachXO2 devices.
But your scenario is much more clear now.

it's took for me less resources when i make this comparison(code above) than if i use the embedded memory.

Click to expand...

Not very sure about that!
Because what the RTL would generate is a comparator and its size depends on the number of inpts. The comp_inputs of the comparator can come from embedded DRAMs, registers formed using LUTs, etc. So I would worry more about the latency in each case.

But as I have no knowledge with Lattice devices, someone else might have a better answer.

In addition to what u said.
I use the BRAM not DRAM.
i tried to use built in comparator from arithmetic modules :

comparator_1 u4(.DataA(pos),.DataB(hu_rise),.AGEB(hu_rise_comp));

put the hu_rise_comp result in the if statement and there is no improvment.