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I'd like to reset my fpga by using pll lock signal.
But I didn't get catch any idea.
So can you let me know how do I reset my FPGA by using pll's lock signal
wrong section. and even when this is moved to FPGA section, why would you use the lock for that? just and the lock with the clock, that behaves safely.
* globally clear/set all used flip flops?
* just add a RESET function to the programmed logic (or a part of it)?
* delete all the programmed functions and program the FPGA anew?
The lock signal which is o/p from the PLL module has some other purpose (read the PLL docu for more info on the lock signal). It should not be used to reset the FPGA. Use the FPGA global async reset signal for reset.
The lock signal which is o/p from the PLL module has some other purpose (read the PLL docu for more info on the lock signal). It should not be used to reset the FPGA. Use the FPGA global async reset signal for reset.
Uh, those "global async reset" signals if they even exist in the currently available FPGAs isn't supposed to be uses to reset any user logic in the FPGA, they are expressly there for post configuration reset to ensure the FPGA comes out of configuration with all the FFs in known states. They are 1. extremely slow and do not meet timing of your clock, 2 are typically accessed in ugly ways like Xilinx's STARTUP block or an external pin on Altera parts (though that might be different now on newer parts).
You also don't want to use a purely asynchronous reset...an asynchronously asserted and synchronously de-asserted reset is normally used.
But the OP may have meant that they want to reprogram the FPGA if the PLL goes out of lock. Based on previous questions posed by the OP, I'm not sure they have done any due diligence by reading the documentation provided by their FPGA vendor of choice.
There are a few tools. The first is the bitgen options. There is an option to hold the global set/reset (GSR) until all used PLL/MMCM/DCM are locked.
Another option is to have a non-pll/mmcm/dcm clock that runs a state machine to ensure all clocks come up.
In that case, you would have a counter to:
1.) hold PLL resets at true for the required time (see datasheet, possibly tens of milliseconds)
2.) hold PLL resets at false for the required pull-in+lock-in times (see datasheet).
3.) repeat if not locked.
4.) otherwise, hold the user-logic reset for a few milliseconds.
5.) allow a controlled de-assertion, with last stage logic deasserting first.
There are a few tools. The first is the bitgen options. There is an option to hold the global set/reset (GSR) until all used PLL/MMCM/DCM are locked.
Another option is to have a non-pll/mmcm/dcm clock that runs a state machine to ensure all clocks come up.
In that case, you would have a counter to:
1.) hold PLL resets at true for the required time (see datasheet, possibly tens of milliseconds)
2.) hold PLL resets at false for the required pull-in+lock-in times (see datasheet).
3.) repeat if not locked.
4.) otherwise, hold the user-logic reset for a few milliseconds.
5.) allow a controlled de-assertion, with last stage logic deasserting first.
This not the 1st time the user "coshy" has done something like this. This member mostly never gives any explanations and keeps the thread dangling (never cares to close them).
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