[Vivado 12-1387] No valid object(s) found for set_max_delay constraint with option

Hi,
I am trying to understand the regular expression as here:
https://www.regular-expressions.info/numericranges.html

and comparing with my critical warning:
[Vivado 12-1387] No valid object(s) found for set_max_delay constraint with option '-to [get_pins -regexp {VOIP/ten_gig_block_kc705/core_reset_dly_reg\[[0-9]\]_srl3__VOIP_ten_gig_block_kc705_core_reset_dly_reg_p_([0-9]|[0-9][0-9])/D}]'.

There is a signal called "core_reset_dly" is defined like this in my program.
signal core_reset_dly : std_logic_vector(7 downto 0);

and as per regular expression(the link above), [0-9] means 0 to 9 and [0-9]|[0-9][0-9]) means either 0 to 9 or 0 to 99.

Then what this critical warning pointing to?

Bitstream is generated succesfully but total negative slack TNS ( -220.412 ns) ans Worst negative Slack WNS -2.358 ns and I assume that this TNS and WNS is due to this critical warning posted avobe.
Any solution?

why are their mixed brackets: core_reset_dly_reg\[[0-9]\] and parenthesis: dly_reg _p_([0-9]|[0-9][0-9]) in your expression? That seems strange.

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also [0-9][0-9][0-9] doesn't match something like 2

002 != 2

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Try it out here

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[0-9]+ should match a multi-digit number that is either 1 character or more, but I think you can also do this with \d+ or something (Tcl might have slightly different syntax for a regex)

ads-ee said:

why are their mixed brackets: core_reset_dly_reg\[[0-9]\] and parenthesis: dly_reg _p_([0-9]|[0-9][0-9]) in your expression? That seems strange.

Click to expand...

This is the constraints from one Xilinx reference design
https://www.xilinx.com/support/documentation/application_notes/xapp1199-smpte2022-56-over-ip.pdf

The XDC constraint is:
set_max_delay -datapath_only -from [get_pins {Si5324CTRL/Si5324_status_reg[0]/C}] -to [get_pins -regexp {VOIP/ten_gig_block_kc705/core_reset_dly_reg\[[0-9]\]_srl3__VOIP_ten_gig_block_kc705_core_reset_dly_reg_p_([0-9]|[0-9][0-9])/D}] 5.400

I myself didn't understand how it is arranged.

Yeah, well I'm not all that impressed by the quality of some of Xilinx's reference designs. Some of them look like output from recent grads that have no experience.

BTW, are you building this with 2015.2? It is always a gamble to use anything but the version that the app note uses.

([0-9]|[0-9][0-9])

The parenthesis are there because of the or. The expression matches either 1 or 2 numbers, but not more.

VOIP/ten_gig_block_kc705/core_reset_dly_reg\[[0-9]\]_srl3__VOIP_ten_gig_block_kc705_core_reset_dly_reg _p_([0-9]|[0-9][0-9])/D

There is a space between "VOIP/ten_gig_block_kc705/core_reset_dly_reg\[[0-9]\]_srl3__VOIP_ten_gig_block_kc705_core_reset_dly_reg" and "_p_([0-9]|[0-9][0-9])/D"

The net may also have a different name in you design, or a different full hierarchy.

ads-ee said:

BTW, are you building this with 2015.2?

Click to expand...

Yes, I am using 2015.2