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Verilog Elevator Control Code

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KatNms

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Hi,

I need help writing the code for a project. It's a three floor building and I have to write the Verilog for an elevator control system and implement it with a FGPA board and a 7-segment display. I need this asap!!! Can someone help??

Thanks!
 

Whats wrong with the code you've already written?
 

I keep getting the following errors:

WARNING:HDLCompiler:413 - "\\ad\eng\users\k\n\knemes\EC311\MiniProject\Elevator.v" Line 69: Result of 8-bit expression is truncated to fit in 7-bit target.
WARNING:HDLCompiler:91 - "\\ad\eng\users\k\n\knemes\EC311\MiniProject\Elevator.v" Line 84: Signal <clk_100> missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result.
WARNING:HDLCompiler:91 - "\\ad\eng\users\k\n\knemes\EC311\MiniProject\Elevator.v" Line 88: Signal <in_current_floor> missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result.
ERROR:HDLCompiler:1511 - "\\ad\eng\users\k\n\knemes\EC311\MiniProject\Elevator.v" Line 37: Mix of blocking and non-blocking assignments to variable <r_out_current_floor> is not a recommended coding practice.
INFO - You can change the severity of this error message to warning using switch -change_error_to_warning "HDLCompiler:1511"
Module Elevator remains a blackbox, due to errors in its contents
WARNING:HDLCompiler:1499 - "\\ad\eng\users\k\n\knemes\EC311\MiniProject\Elevator.v" Line 21: Empty module <Elevator> remains a black box.
Click to expand...

Additionally, I'm not 100% certain my code does what it's supposed to, but from what I got from the test fixture, it looked right. I'm trying to implement on a FGPA board using Xilinx but whenever I try to generate the programming file I get those errors. Do you know how I can fix them? Or if there are any other errors I need to fix in order to finish my project correctly?

This is my code thus far...

Code Verilog - [expand]
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module Elevator(request_floor, in_current_floor, clk, reset, complete, direction, out_current_floor);
 
//input pins
input [2:0] request_floor; //3 bit input floor request
input [2:0] in_current_floor; //3 bit input request floor;
input clk;
input reset; //1 bit input reset
 
//output pins
output [2:0] out_current_floor; //3 bit output showing current floor
output direction; //1 bit output indicates if elevator is going up or down
output complete; //1 bit output indicates if elevator is stopped or running
 
//register parameters
reg r_direction; //1 bit reg connected to direction
reg r_complete; //1 bit connected to complete;
reg [2:0] r_out_current_floor; //3 bit reg connected to out_current_floor
 
 
//clock generator register
reg [6:0] clk_count;
reg clk_100;
reg clk_trigger;
 
//match pins and registers
assign direction = r_direction;
assign complete = r_complete;
assign out_current_floor = r_out_current_floor;
 
//initialization
 
always @ (negedge reset) //will only run when reset = 0, reset CLK_100, CLK_count, and CLK_trigger to 0
 
    begin
    
    clk_100 = 1'b0;
    clk_count = 0;
    clk_trigger = 1'b0;
    
    //reset the clock registers
    r_complete= 1'b0;
end
    
//clock generator block
always @ (posedge clk) begin
    
    if (clk_trigger) 
        begin
        clk_count = clk_count +1;
    end
    if (clk_count == 5000) begin
        clk_100 =~ clk_100;
        clk_count = 0;
    end
    
end
 
//requested floor
 
always @ (request_floor) 
    begin
    
    clk_trigger =1 ;
    clk_100 =~ clk_100;
 
    //trigger clock generator
    
    r_out_current_floor <= in_current_floor;
end
 
//3 cases for elevator
 
always @ (posedge clk) begin
 
if (!reset)
    begin
    
    if (request_floor > r_out_current_floor) begin
    r_direction = 1'b1;
    
    r_out_current_floor <= r_out_current_floor << 1;
    end
    
    else if (request_floor < r_out_current_floor) begin
    r_direction = 1'b0;
    r_out_current_floor = r_out_current_floor >> 1;
    end
    
    else if (request_floor == r_out_current_floor) begin
    r_complete = 1;
    r_direction = 0;
    end
end
 
end
 
endmodule

The test fixture...

Code Verilog - [expand]
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module Elevator_Test;
 
    // Inputs
    reg [2:0] request_floor;
    reg [2:0] in_current_floor;
    reg clk;
    reg reset;
 
    // Outputs
    wire complete;
    wire direction;
    wire [2:0] out_current_floor;
 
    // Instantiate the Unit Under Test (UUT)
    Elevator uut (
        .request_floor(request_floor), 
        .in_current_floor(in_current_floor), 
        .clk(clk), 
        .reset(reset), 
        .complete(complete), 
        .direction(direction), 
        .out_current_floor(out_current_floor)
    );
 
    initial begin
        // Initialize Inputs
        request_floor = 0;
        in_current_floor = 0;
        clk = 0;
        reset = 0;
 
        // Wait 100 ns for global reset to finish
        #100;
        
        // Add stimulus here
            #0 clk = 1'b0; reset = 1'b1; 
    #50 reset = 1'b0;
    #50 reset = 1'b1;
    #50 request_floor = 3'b001; in_current_floor = 3'b100;
    #50 reset = 1;
    #50 reset = 0;
    #50 request_floor = 3'b001; in_current_floor = 3'b100;
    #50 reset = 1'b1;
    #50 reset = 1'b0;
    end
    
    always #50 clk = ~clk;
   
endmodule
 
Last edited by a moderator:

First off, please post your code with either code tags or syntax tags. I cannot easily match up the errors with the code. But there are a few obvious things

1. I cant tell which line is the truncation warning, but I know this is impossible, as clk_count is only a 6 bit number (0 -127)
clk_count == 5000
This also shows you have clk_100 driven in two different always blocks

2. The //requested floor process is asynchronous, and also drives clk_100 with the inverse of itself, so needs to be in the sensitivity list for the warning, but in reality you should remove this signal from this always block altogether.

3. As above. It's asynchronous logic, in_current_floor is needed in the //requested floor always block.

4. Mixing blocking (=) and non-blocking assignments is pretty bad. Just dont do it. Always use non-blocking assignments (<=) inside always blocks for now.
 
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    K

    KatNms

    Points: 2
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Besides everything Tricky has mentioned, you should go look at the synthesis coding guidelines from Altera/Xilinx and use the templates they provide for flip-flops etc.

Things like r_complete getting set but never clearing are a problem too, besides that you have all the reset code in another always block making then automatically multiple drivers on those signals.
 

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