comparing values of memory locations

please someone give me an idea about how to design a hardware to compare the data of a block ram and to keep the equal valued data in another ram. Actually i can do it , but my main problem is if i make it clock dependant , then the process wits for rising_edge of clock to start or to restart hence making the process slow. but without clock i cant move on to the next location because i think increment of memory location code will use a counter which in turn will use clock. If i have no provision to increase clock frequency then is there any way to serve my purpose . I need to complete the entire process in 100 ns , i need to compare almost 1000 data by that time else next dataset will come and will replace this dataset . My board clock frequency is 20 ns . I f i wait for clock i can hardly complete 5 iterations aftr which new dataset will arrive . I just need an idea , i will implement it myself .

FPGA internal RAM can access one or maximal two (by using dual port RAM) locations per clock cycle. In so far it's not feasible to perform the intended comparison with 1000 RAM locations in 5 or 10 clock cycles.

Distributed RAM can work faster, but as it's implemented in logic elements, it involves a large amount of FPGA resources.
Another option would be a content addressed memory (CAM) design, it can be feasible if the data word length isn't too large.

From what I can tell, the problem is to take a list of N numbers and find the duplicates. I'm not sure if the output will also contain duplicates if there are triplicates in the input.

A straightforward approach takes around 500k comparisons. If the input is sorted, this drops to around 1k. This doesn't include logic for handling the input or output.

1E3 / 100E-9 = 1E10. This means 10Gbps per bit of width.


@p11, are these actual requirements, or just numbers you intend to reach? You already don't understand that the issue is less that you are waiting on a clock vs a highly unrolled design would not actually fit on any device. That input/output bandwidths are 10Gbps+ and you are discussing only using a 50MHz clock, I'm really wondering where these requirements come from?

p11 said:

please someone give me an idea about how to design a hardware to compare the data of a block ram and to keep the equal valued data in another ram. Actually i can do it , but my main problem is if i make it clock dependant , then the process wits for rising_edge of clock to start or to restart hence making the process slow. but without clock i cant move on to the next location because i think increment of memory location code will use a counter which in turn will use clock. If i have no provision to increase clock frequency then is there any way to serve my purpose . I need to complete the entire process in 100 ns , i need to compare almost 1000 data by that time else next dataset will come and will replace this dataset . My board clock frequency is 20 ns . I f i wait for clock i can hardly complete 5 iterations aftr which new dataset will arrive . I just need an idea , i will implement it myself .

Click to expand...

I wonder if you work for a company and if they actually put products out with your code in it. your understanding of hardware and digital design is bizarre.

ThisIsNotSam said:

I wonder if you work for a company and if they actually put products out with your code in it. your understanding of hardware and digital design is bizarre.

Click to expand...

i dont understand why you always come to do nonsense ... if you cant give idea , stay away from my posts , because i an a civilised person and dont want uncivilised ppl around me ... stay away for God's sake ...and again am repeating for everyone here , if you can help me then only comment else i wont mind if anyone dont answer me , bt yes if you want to get insulted again then obviously come , i will like to teach ppl like you to get civilised in true form .you dont have minimum respect for others and you think yourself knowledgeable. .. you really need blessing along with some hard lessons like the one am giving right now ...

and yes , try to motivate people because your single word can demotivate others ... your word speaks about you even much more than your knowledge so i warn you mind your language further ... remember i warn you .idiots ....and this comment is for everyone who did or are going to do nonsense again ...

Edaboard moderators use to delete contributions like the last two post as off-topic and purposeless arguing. If we agree that the off-topic discussion should be stopped now, I'll keep it as a reminder to stay technical. Hope co-moderators don't beat me for it. If the discussion goes on this way, I'll delete all off-topic posts including mine and issue infractions.

p11, you already had a thread on this subject, (I should issue an infraction for this violation of the forum rules). Maybe you should go back and READ the posts on that thread. Specifically the second half of post #10, but you probably didn't read the reset of the post as I questioned your qualifications.

Basically what you are asking to do might be possible based on the explanation I gave or impossible if you insist on using block RAM. I also made a suggestion earlier to use flip-flops with no RAM usage at all. Either method will require extensive logic to perform the comparisons in parallel and perhaps a lot of duplicated logic to do this in the minimum number of clock cycles (5) to meet your timing budget. It would be better if you can increase the clock frequency through a PLL from the 50 MHz to use use less resources and give yourself some extra clock cycles to work with.