The likely scenario is they are using an FPGA board to control the LTC2607 DAC so we need to know what the LTC2607 daughter board is and see the code and testbench for the FPGA interface to that daughter card to help.
// i2c main module
`timescale 1ns / 1ps
module fpga_i2c1(
input clk,
input reset,
//inout reg i2c_select,
inout reg i2c_sda,
inout wire i2c_scl
);
localparam I2C_IDLE=0;
localparam I2C_START=1;
localparam I2C_ADDR=2;
localparam I2C_ACK1=3;
localparam I2C_COMD=4;
localparam I2C_ACK2=5;
localparam I2C_DAT1=6;
localparam I2C_ACK3=7;
localparam I2C_DAT2=8;
localparam I2C_ACK4=9;
localparam I2C_STOP=10;
localparam I2C_STOP1=11;
localparam I2C_STOP2=12;
reg [5:0] count;
reg [3:0] state;
reg i2c_scl_enable ;
reg [31:0] work_in_data;
assign i2c_scl = (i2c_scl_enable == 0 )?1:~clk ;//i2c clock for start & stop condition
//i2c clock start and stop
always@(negedge clk) begin
if(reset==0)begin
i2c_scl_enable <= 0;
end else begin
if(state==I2C_IDLE || state == I2C_STOP || state == I2C_START || state == I2C_STOP1) begin
i2c_scl_enable <= 0;
end else begin
i2c_scl_enable <= 1;
end
end
end
//state machine for i2c protocol
always@(posedge clk) begin
if(reset==0) begin
state <=0;
i2c_sda <=1;
work_in_data <=0;
count <=0;
end else begin
case (state)
I2C_IDLE: begin //idle state
i2c_sda <= 1;
state<= I2C_START;
work_in_data <= 32'b11100110001111111111110001100111;;
end
I2C_START: begin //start
i2c_sda <=0;
state<= I2C_ADDR;
count<=6'b011111;
end
I2C_ADDR: begin //sending slave address
i2c_sda <= work_in_data[count];
if(count==6'b011000)begin
state <= I2C_ACK1;
count<= count-1;
end else begin
count<= count-1;
end
end
I2C_ACK1: begin //acknowledgement 1
i2c_sda<= 0;
state <= I2C_COMD;
end
I2C_COMD : begin //sending command
i2c_sda <= work_in_data[count];
if(count==6'b010000)begin
state <= I2C_ACK2;
count<= count-1;
end else begin
count<= count-1;
end
end
I2C_ACK2: begin //acknowledgement 2
i2c_sda<= 0;
state <= I2C_DAT1;
end
I2C_DAT1: begin // first 8 bit data
i2c_sda <= work_in_data[count];
if(count==6'b001000)begin
state <= I2C_ACK3;
count<= count-1;
end else begin
count<= count-1;
end
end
I2C_ACK3: begin //acknowledgement 3
i2c_sda<= 0;
state <= I2C_DAT2;
end
I2C_DAT2: begin //sending 2nd 8 bit data
i2c_sda <= work_in_data[count];
if(count==0)begin
state <= I2C_ACK4;
end else begin
count<= count-1;
end
end
I2C_ACK4: begin //acknowledgement 4
i2c_sda<= 0;
state <= I2C_STOP;
end
I2C_STOP : begin //stop condition
i2c_sda<= 0;
state <= I2C_STOP1;
end
I2C_STOP1 : begin //stop condition1
i2c_sda<= 1;
state <= I2C_IDLE;
end
/* I2C_STOP2 : begin //stop condition1
i2c_sda<= 1;
state <= I2C_STOP1;
end */
endcase
end
end
endmodule// i2c main module
`timescale 1ns / 1ps
module fpga_i2c2 ;
wire i2c_sda;
wire i2c_scl;
//wire d_clk;
reg reset;
reg clk;
clock uut2(
.clk(clk),
.reset(reset),
.i2c_sda(i2c_sda),
.i2c_scl(i2c_scl),
.d1_clk()
);
initial begin
clk =0;
reset =0;
#100000
reset = 1;
end
always begin
#10 clk <= ~clk;
end
endmodule`timescale 1ns / 1ps
module clock (
input clk,
input reset,
inout i2c_sda,
inout i2c_scl,
output d1_clk
);
fpga_i2c1 uut(
.clk(d1_clk),
.reset(reset),
.i2c_sda(i2c_sda),
.i2c_scl(i2c_scl)
);
reg d_clk;
//wire d1_clk;
reg [9:0]counter;
reg r_reset;
assign d1_clk = d_clk;
always@(negedge clk) begin
if(reset==0 )begin
counter<=0;
d_clk <=1;
r_reset <=1;
end
if(reset==1 || r_reset ==1) begin
counter<=counter+1;
end
if(counter==10'b0111111111) begin
counter<=0;
d_clk <= ~d_clk;
end
end
endmodule
if(counter==10'b0111111111) beginwork_in_data <= 32'b11100110001111111111110001100111;;
I2C_START: begin //start
count<=6'b011111;
end
I2C_ADDR: begin //sending slave address
i2c_sda <= work_in_data[count];{i2c_sda, work_in_data} <= {work_in_data[31:0], 1'b0};Doesn't the DAC User Manual or the Datasheet describe the maximum allowed input voltage? Or is this some low cost Chinese board with virtually no documentation?i am also suspecting the same ads-ee, so is there any way to know to it, because i f i know it, at least i can buy an another board. it will save some time for me
In DAC USER MANUL describes it using it with another fpga board, which describes connecting it through a software came along with the fpga ( which in dont have). so any little help is much appriciated
Thanks and Regards
Code Verilog - [expand]
Code Verilog - [expand]