[SOLVED] Memory Initialization File for Xilinx FPGA boards using .coe file

For Altera we use the following to initialize the memory

type mem_t is array(0 to 255) of unsigned(7 downto 0);
signal ram : mem_t;
attribute ram_init_file : string;
attribute ram_init_file of ram :
signal is "my_init_file.mif";
However, for xilinx we have .coe files for initialization rather than .mif
I have created the coefficient file in .coe format, now I need to access that in the main code for memory. How can I do that in xilinx using VHDL?

If you had created your BRAM memory using the Block Memory Generator you would have gotten a simulation file that already has the data as a set of (I think) generics called INIT_x = xxxxxxxxxx...xxxxxxxxxxxxx that have the data you had read in from a .coe file when generating the core, otherwise you would use something similar to what is described here, which looks like what you are doing with Altera already as it appears your intention is to infer your RAM.

Generate block RAM, ROM or distributed RAM through IP cores, i.e. automatic generation through wizard. it will ask you for the path of the .coe file, give it the path and your memory will be loaded with the data

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ads-ee said:

If you had created your BRAM memory using the Block Memory Generator you would have gotten a simulation file that already has the data as a set of (I think) generics called INIT_x = xxxxxxxxxx...xxxxxxxxxxxxx that have the data you had read in from a .coe file when generating the core, otherwise you would use something similar to what is described here, which looks like what you are doing with Altera already as it appears your intention is to infer your RAM.

Click to expand...

$readmemh("mem_init_vlog.mif", mem, 0, 255); is not the synthesizable statement while .coe is

fouwad said:

$readmemh("mem_init_vlog.mif", mem, 0, 255); is not the synthesizable statement while .coe is

Click to expand...

Wow, cherry pick statements and claim I'm suggesting the above? So why did you point this out like I was suggesting to use this?. FYI, In some instances readmemh is synthesizable just look at both Xilinx's and Altera's synthesis guidelines. Here is an AR that describes using $readmemh to intialize an inferred block ram. http://www.xilinx.com/support/answers/62935.html

mif and coe are just two file formats that describe the same thing, the contents of a memory, whether or not they are useful for synthesis is dependent on whether they are compatible with whatever the synthesis tool requires. $readmemh requires a file of hex values with all addresses defined and I believe no headers are allowed. The .coe file is a block ram generator tool input file that has header information besides all the binary data for the RAM based on the address locations given by the .coe file it is also NOT synthesizable, but is converted into those INIT_x statements I mentioned previously.