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VHDL - Register from Procedure ??

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jinbow

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Hi All,

Is it ok to have a Register made out of a Procedure (sub program) in VHDL?? Is it synthesizable??

EXAMPLE:
Code: 
[syntax=vhdl]
procedure REG
        (signal	clk			: in	std_logic;
	signal        d			: in	std_logic;
	signal        q			: out	std_logic)
is begin
	if rising_edge(clk) then
		q <= d;
	end if;
end procedure;
[/syntax]

Can this be called directly inside the Architecture or does it have to be called inside a Process??
Will both cases be synthesized as an actual Register technology?? And can this be used universally for all vendors/tools??

I'm a bit confused since usually when a register is declared inside a Process(clk), a sensitivity list is used to execute the process whenever clk changes.
But if it is called under the Architecture without a Process, there won't be a sensitivity list.
Although in this code, it doesn't matter since it will only be executed under the rising_edge(clk).
Just want to get your thoughts, please advise.

Thanks,
ALbert
 

It's legal VHDL inferring a register and can be called in concurrent code, without a process.

Similar constructs can be often found in test benches, but I don't see a reason to use it in VHDL for synthesis.
 

This will work, but you will have to call it from a process to actually work. While it can be called from a function, functions cannot have any notions of time inside them (eg using wait statements) and execute in a single delta cycle, so this process would always return without assigning d to q. The only way you procedure would actually work would be in this code:

Code VHDL - [expand]
1
2
3
4

process(clk)
begin
  REG(clk, d, q);
end process;


As for synthesis, I would say that all should support it - but dont be surprised if older tools choke on it. There are no rules governing what can and cannot be synthesised - its down to the vendors.
 

As for synthesis, Altera Quartus does infer a register, without a process.
 

FvM said:
As for synthesis, Altera Quartus does infer a register, without a process.
Click to expand...

Actually that does make sense - I had forgotten that single line statements infer a process.
 

I can see where it could be used. I think the main benefit is that procedures can be impure. Thus, you could have a default clock/reset without needing a port map. This is a minor point though.

In general, I feel procedures can be very useful for inferring logic.
 

I can see where it could be used. I think the main benefit is that procedures can be impure. Thus, you could have a default clock/reset without needing a port map. This is a minor point though.

In general, I feel procedures can be very useful for inferring logic
Click to expand...
.
I feel that we better shouldn't use it to synthesize synchronous logic. And I don't see a specific advantage over the recommended templates for register interference. These impure procedures are really convenient in test benches. I have e.g. write_bus() and read_bus() procedures that mimic an external processor driving a memory mapped interface to setup various parameters of a design.

Before verifying correct register synthesis in Quartus, I was not so sure that it would work with the tool, and I'm still not sure with other tools, I agree with TrickyDicky in this point.

As for synthesis, I would say that all should support it - but dont be surprised if older tools choke on it. There are no rules governing what can and cannot be synthesised - its down to the vendors.
Click to expand...
 

Hi All,

Thanks for all the comments and information.

FYI.
Both devices/tools, listed below, did properly infer that Procedure as a Register without a Process (called directly under Architecture).
Microsemi (Actel) - ProAsic3 using Libero
Xilinx - Kintex using Vivado


Thanks,
ALbert
 

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