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[moved] VerilogA in Cadence Virtuoso

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Pavlanto

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Hi,
I have written a VerilogA code for a track and hold circuit. I simulate it (by using the symbol view) and it runts properly. Is there a way that i can handle a circuit or work at least some layout from the code i have written? Is there really an analog circuit behind my code or is it just the code running ?
Thanks
 

you can do some schematic to layout automation, but it is not a full solution. you still need to do lots of work by hand.
 

My main question is:do we have something behind the code?? I just have the code in verilogA and a symbol which represents the code i wrote. I couldnt find something more than that!
P.S My code is for an analog device!
 

Pavlanto said:
My main question is:do we have something behind the code?? I just have the code in verilogA and a symbol which represents the code i wrote. I couldnt find something more than that!
P.S My code is for an analog device!
Click to expand...

there is no way for someone to know what you have or what you don't have. if you wrote a verilogA code, then it is a code and that's it. if you got this from a library somewhere, then maybe there is more files that come with it. your question is vague, I don't know how to answer better than this.
 

Up to now VerilogA is used rather to modeling and simulation of analog circuits. It is hard to synthetize schematic/layout from such code. I have read that there were some tries to do such tools.
 

Schematic to layout (given a suitably constructed primitives
library) is offered (some assembly required). Code to layout,
I have never seen in the analog realm. Structural verilog
/ veriloga (where every element at the lowest level is a
real component, transistor / resistor / capacitor, call and
no "loop" or such constructs, might be massaged into a
netlist for at least auto-placement and flight lines (which
is about all you get from schematic-to-layout). But a pure
code-monkey anything-legal-goes kind of veriloga, forget it.
 

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