rangicut
Newbie level 2
Hi, everyone!
Can someone help me with one strange thing in the documentation of Xilinx Spartan 3 FPGAs.
I have an old PCB with Spartan 3E FPGA. The device realizes some DSP and arithmetic algorithms. My task is to optimize them in means of area.
I've opened this FPGA datasheet (ds312 - https://www.xilinx.com/support/documentation/data_sheets/ds312.pdf) and found strange shematic of the implementation of carry logic for one-bit full adder using logic cell's 2-1 mux (p. 30 fig. 23 Using the MUXCY and XORCY in the Carry Logic). I see here a mistake - the zero input of the MUX should be loaded by "A and B", not by only "A".
Am I right?
Thanks.
Can someone help me with one strange thing in the documentation of Xilinx Spartan 3 FPGAs.
I have an old PCB with Spartan 3E FPGA. The device realizes some DSP and arithmetic algorithms. My task is to optimize them in means of area.
I've opened this FPGA datasheet (ds312 - https://www.xilinx.com/support/documentation/data_sheets/ds312.pdf) and found strange shematic of the implementation of carry logic for one-bit full adder using logic cell's 2-1 mux (p. 30 fig. 23 Using the MUXCY and XORCY in the Carry Logic). I see here a mistake - the zero input of the MUX should be loaded by "A and B", not by only "A".
Am I right?
Thanks.