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ASYNCHRONOUS FIFO ISSUE: using Dual port RAM vs Flip Flops as FIFO MEMORY

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abhinavpr

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Hi ,
is using Flip flops as FIFO memory in an ASYNCHRONOUS FIFO a standard practice in the industry?. For smaller fifo sizes like 8-16 depths fifo inferred memory should be used.
but flop inferred memory will have non registered output and that would result in getting the read data in the same cycle in which rd_en is placed.
what would the solution be?
register the output data by adding additional flop stage or change the controlling logic?


-abhinavpr
 

if you need registered output, you register the output.
if you don't, you don't.

it doesn't matter if the FIFO is built with flops or sram.
 

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