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Can a latch be used as a flop by modifying its enable input?

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Ashish Agrawal

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Hi Experts,

Can this circuit be used as a flop?

latch_as_flop.png

Basically, I have delayed the clock signal and ANDed it with the original clock signal. The output of AND is used as Enable to latch. So instead of having the Enable high for long duration, it will be equivalent to delay of BUFFERs.
If we are able to provide delay of BUFFERs equal to setup time of latch ( setup time will be measured with respect to negative edge/closing edge) then will this circuit work as an edge-triggered flop?
Is it really possible to provide this exact delay? If not, why?

Regards,
Ashish
 

Ashish Agrawal said:
Hi Experts,

Can this circuit be used as a flop?

View attachment 130364

Basically, I have delayed the clock signal and ANDed it with the original clock signal. The output of AND is used as Enable to latch. So instead of having the Enable high for long duration, it will be equivalent to delay of BUFFERs.
If we are able to provide delay of BUFFERs equal to setup time of latch ( setup time will be measured with respect to negative edge/closing edge) then will this circuit work as an edge-triggered flop?
Is it really possible to provide this exact delay? If not, why?

Regards,
Ashish
Click to expand...

One correction is required, not able to edit the same post. so replying.
"Please consider the BUFFERs as ODD number of inverters."

Regards,
Ashish
 

Can you tell us what the minimum guaranteed clock pulse width will be over all corners of Process,Voltage and Temperature for any layout?

If you cannot then you shouldn't try to build your own delay lines.

John Eaton
 

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