Anwesa Roy
Member level 2
We are designing LMS algorithm using vhdl.
We want to know how each value of X comes. We have been told that X is a complex number, which is the input to equalizer which comes AFTER TRAVELLING THROUGH the CHANNEL suffering from noise, pathloss etc.So the question is , will we get the value of X(1) after first delay, X(2) after 2nd delay and so on.
But, in design through vhdl how can we design a channel that will contain noise,delay, pathloss etc (example a Rayleigh fading channel).
Our senior has designed the LMS algorithm through hardware cosimulation where she has modelled the channel using Rayleigh fading channel. But we are unsure if such a design could be done in vhdl.So we cant find a value of X [input signal] and d [desired signal] with which we can simulate our vhdl program.
We have designed an algorithm, but we dont know what value should we take for x(0), x(1),.....x or d...
We have taken four values of x, and used these values iteratively..Is the process correct(Since the calculations involes complex numbers, we have broken the complex and real parts and have computed those individually)...Another question is that, d is just one signal, however x is so many...why is that?...
We want to know how each value of X comes. We have been told that X is a complex number, which is the input to equalizer which comes AFTER TRAVELLING THROUGH the CHANNEL suffering from noise, pathloss etc.So the question is , will we get the value of X(1) after first delay, X(2) after 2nd delay and so on.
But, in design through vhdl how can we design a channel that will contain noise,delay, pathloss etc (example a Rayleigh fading channel).
Our senior has designed the LMS algorithm through hardware cosimulation where she has modelled the channel using Rayleigh fading channel. But we are unsure if such a design could be done in vhdl.So we cant find a value of X [input signal] and d [desired signal] with which we can simulate our vhdl program.
We have designed an algorithm, but we dont know what value should we take for x(0), x(1),.....x or d...
We have taken four values of x, and used these values iteratively..Is the process correct(Since the calculations involes complex numbers, we have broken the complex and real parts and have computed those individually)...Another question is that, d is just one signal, however x is so many...why is that?...
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lms2 is
Port (wr9,wi9,xr,xi : in STD_LOGIC_VECTOR (12 downto 0);
--u : in integer;
yr,yi,er,ei,wr8,wi8,zzz,sum1 : out STD_LOGIC_VECTOR (12 downto 0));
end lms2;
architecture Behavioral of lms2 is
signal a,b :real;
signal yr11, yi11, yr22, yi22 : real;
--variable r,s : real range 0.0 to 15.0;
begin
process(wr9,wi9,xr,xi)--process also runs without the parameters,but it gives problems during simulation
--process(u,xr,xi)
variable wr : std_logic_vector(12 downto 0);
variable wi : std_logic_vector(12 downto 0);
--variable wr : std_logic_vector(4 downto 0) :="00010";
--variable wi : std_logic_vector(4 downto 0) :="00011";
--variable wr : std_logic_vector(4 downto 0) :=wr9;
--variable wi : std_logic_vector(4 downto 0) :=wi9;
variable xr1_1 : real :=0.707;
variable xi1_1 : real :=0.701;
variable xr1_2 : real :=0.707;
variable xi1_2 : real :=0.701;
variable xr_0 : real :=0.707;
variable xi_0 : real :=0.701;
variable xr_1 : real :=0.707;
variable xi_1 : real :=0.701;
variable xr_2 : real :=0.707;
variable xi_2 : real :=0.701;
variable xr_3 : real :=0.707;
variable xi_3 : real :=0.701;
variable dr1 : real :=0.807;
variable di1 : real :=0.801;
variable yr1_1: real;
variable yi1_1 : real;
variable yr1_2 : real;
variable yi1_2 : real;
variable er1_1 : real;
variable ei1_1 : real;
variable er1_2 : real;
variable ei1_2 : real;
variable wr1_1 : real := 0.0;
variable wi1_1 : real := 0.0;
variable wr1_2 : real := 0.0;
variable wi1_2 : real := 0.0;
variable u : real :=0.2;
variable k : integer :=0;
--variable f : real := 3.2;
--variable g : real := 2.6;
--variable h : real;
--variable hh : real;
begin
--h := f+g;
--hh := f*g;
--a <= h;
--b <=hh;
--process(xr,xi,u)
--bi <= to_integer(unsigned(k)) ;
--bj <= to_integer(unsigned(l)) ;
--bk <= bi*bj;
for z in 1 to 170 loop
if (k=0)then
xr1_1 := xr_0;
xi1_1 := xi_0;
xr1_2 := xr_3;
xr1_2 := xi_3;
elsif (k=1) then
xr1_1 := xr_1;
xi1_1 := xi_1;
xr1_2 := xr_0;
xr1_2 := xi_0;
elsif (k=2) then
xr1_1 := xr_2;
xi1_1 := xi_2;
xr1_2 := xr_1;
xr1_2 := xi_1;
elsif (k=3) then
xr1_1 := xr_3;
xi1_1 := xi_3;
xr1_2 := xr_2;
xr1_2 := xi_2;
end if;
k := k+1;
if(k=4) then
k := 0;
end if;
yr1_1 := wr1_1*xr1_1-wi1_1*xi1_1;
yi1_1 := wr1_1*xi1_1+wi1_1*xr1_1;
yr1_2 := wr1_2*xr1_2-wi1_2*xi1_2;
yi1_2 := wr1_2*xi1_2+wi1_2*xr1_2;
er1_1 := (wr1_1*xr1_1)-(wi1_1*xi1_1)-dr1;
ei1_1 := (wr1_1*xi1_1)+(wi1_1*xr1_1)-di1;
er1_2 := (wr1_2*xr1_2)-(wi1_2*xi1_2)-dr1;
ei1_2 := (wr1_2*xi1_2)+(wi1_2*xr1_2)-di1;
wr1_1 := u*(xr1_1*er1_1-xi1_1*ei1_1)+wr1_1;
wi1_1 := u*(xr1_1*ei1_1+xi1_1*er1_1)+wi1_1;
wr1_2 := u*(xr1_2*er1_2-xi1_2*ei1_2)+wr1_2;
wi1_2 := u*(xr1_2*ei1_2+xi1_2*er1_2)+wi1_2;
end loop;
yr11 <= yr1_1;
yi11 <= yi1_1;
yr22 <= yr1_2;
yi22 <= yi1_2;
end process;
end Behavioral;
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