DustHerder
Newbie level 4
Hi guys,
If I select a net in a verilog module, is it possible to find the primary inputs that my net depend in DesignCompiler?
I already tried the report_transitive_fanin but i have registers in my circuit and this command have a problem because the fanin report stops at the clock pins of registers.
Thanks,
DustHerder
If I select a net in a verilog module, is it possible to find the primary inputs that my net depend in DesignCompiler?
I already tried the report_transitive_fanin but i have registers in my circuit and this command have a problem because the fanin report stops at the clock pins of registers.
Thanks,
DustHerder
