Modeling issue for charging and discharging the capacitor

As we know, when using constant voltage to charge the RC circuit. We can get the following result.



Changing the resistance will change the time constant influencing the rising time and falling time.

Another situation is to use constant current to charge the capacitor. Here is my issue.



Constant current uses a switch to control charging the capacitor. For the ideal switch, no matter when it turns off/on, the voltage is kept increasing. This is because when switch on, the current goes through a small resistor and charge the capacitor. When switch off, the current goes through a huge resistor but still charge the capacitor with a small current.
However, when using NMOS transistor as the switch, the voltage behaves as a step signal. When the clock signal goes high, the voltage of the capacitor steps high immediately. When the clock signal stays high, the voltage is increasing linearly. When the clock signal goes to GND, the voltage also steps down a lot.


Does anybody know how to explain this simulation?
Thank you very much.
leonard

Do you find the capacitor discharges back through the mosfet while it is turned off?

Please include rise- and falltimes to your clock signal.

Discharge back?
Clock feed-through is more reasonable, yes?
When the clock goes down, the CGS of the MOSFET will bring the charge sharing between CGS and Cload. And then the voltage will reduce.
My question is when the clock goes high, the voltage of the capacitor is increasing immediately. How to explain?

Your schematics show a tiny capacitor that has almost no capacitance. Why not use a real capacitor that has a billion times the capacitance?

The rising time and falling time is 10ps and it is added on the spice model.

Audioguru said:

Your schematics show a tiny capacitor that has almost no capacitance. Why not use a real capacitor that has a billion times the capacitance?

Click to expand...

When the capacitance was changed, the step situation doesn't change. It still step up when the NMOS turns on. But the delta voltage is changed.

leonardwu said:

..............
My question is when the clock goes high, the voltage of the capacitor is increasing immediately. How to explain?

Click to expand...

It does not do it "immediately", just in a very short time since the charging R of the MOSFET ON resistance is very low and the capacitor is also very small, making for a very fast RC time-constant.
Try a larger capacitor value and you will see will more readily see the finite charge time.

If you turn off the charging circuit at a constant current, the voltage will rise to infinity because it will still try to maintain the charging current. This is similar to shorting a constant voltage source that will try to supply infinite current through the load.

The trick is to introduce small resistances / capacitances (as appropriate) so that the singularity arising from the turning on/off is avoided.

The voltage step effect is known as "charge injection" through gate capacitance and will be observed with any real analog switch. The effect is considerably lower for CMOS switches where NMOS and PMOS transistors are controlled by complementary gate voltages so that the injected charges cancel mostly.

An additional positive voltage step on the switch-on edge is caused by discharging the floating current source output. I agree with c_mitra that switching a current source by SPST switch without clamping isn't a reasonable topology. Currents are preferably switched by SPDT switches, keeping a continuous current source output.

I use cadence to model a current mirror to charge the capacitor. And I found the simulation has a big step in the first time and then other steps are almost equal. I don't why

leonardwu said:

Constant current uses a switch to control charging the capacitor. For the ideal switch, no matter when it turns off/on, the voltage is kept increasing.

Click to expand...

Follow the same way as you would do with voltage pulses.

(for voltage pulse charging and discharging)

1. From 0V, raise voltage to V (you need to introduce some resistance so that a time constant may be defined)
2. The capacitor charges exponentially to voltage V
3. After time t, reset the voltage to 0V
4. The capacitor discharges exponentially to 0V

(for const current charging)

1. Apply a const current to the capacitor (through a resistor, of course)
2. The cap charges up linearly to infinite voltage
3. After time t, reverse the current (may not be same value)
4. The capacitor discharges to minus infinity (goes via zero)

Now you can see the reasons for the slopes and offsets in your simulations...

Getting back to a post #1 question.

For the ideal switch, no matter when it turns off/on, the voltage is kept increasing.

Click to expand...

The switch isn't ideal, the default model has a non-infinite Roff, review the simulator manual. Thus the source current flows continuously, ignoring switch on or off state. A completely unrealistic simulation due to the ideal current source and switch with zero capacitance.

I use cadence to model a current mirror to charge the capacitor. And I found the simulation has a big step in the first time and then other steps are almost equal. I don't why

Click to expand...

I presume you'll see if you monitor the MOSFET drain voltage.

To say it again, the combination of current source and single (SPST) switch is no reasonable circuit topology.