fellipefepp
Newbie level 1
My ADC structure uses a loop and I do not know why Simulink complain about it. I have the following situation:
I have a Sample and Hold (SH A) cell controlled by a combinational logic and its output is used as input in another Sample and Hold cell (SH B). Besides that, SH B's output is used as one of the input that control SH A's clock. Basically, I have a loop between two SH. After I try to simulate it shows:
"Ambiguous sorted order detected due to use of triggered subsystem(s) and/or Model blocks in a loop. See Subsystem Examples in the Simulink library for valid and invalid examples of triggered subsystems"
To "solve" this problem I checked the option "...input buffer" in SH B. If I do this, I do not have this problem anymore, but since my result will be missing one sample every period. There is a way to solve this without delaying SH B output ? Its not necessary to use SH cell, but I need something to store data controlled by a clock signal.
I have a Sample and Hold (SH A) cell controlled by a combinational logic and its output is used as input in another Sample and Hold cell (SH B). Besides that, SH B's output is used as one of the input that control SH A's clock. Basically, I have a loop between two SH. After I try to simulate it shows:
"Ambiguous sorted order detected due to use of triggered subsystem(s) and/or Model blocks in a loop. See Subsystem Examples in the Simulink library for valid and invalid examples of triggered subsystems"
To "solve" this problem I checked the option "...input buffer" in SH B. If I do this, I do not have this problem anymore, but since my result will be missing one sample every period. There is a way to solve this without delaying SH B output ? Its not necessary to use SH cell, but I need something to store data controlled by a clock signal.