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Process in VHDL code

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MSAKARIM

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I read that inside the "process" statement in VHDL the commands are executed sequentially, but still this code gives me error and need C to be inout
Code: 
entity mmm is
port (a,b: in bit;
c,d:out bit);
end mmm;

architecture Behavioral of mmm is

begin
process (a,b)
begin
c<= a and b;
d<= c or b;
end process;
end Behavioral;
 

You are using output signal c as input for output signal d.

If you really need "a and b" product for d you can do next:
Code: 
 c <= a and b;
    d <= (a and b) or b;

Or use c as "inout" port.

Also, you can do this thing:

Code: 
e <= a and b;
c <= e;
d <= e or b;
 

Reading out ports has nothing to do with processes.
You can:
- use VHDL-2008 which allows readback of out ports
- use buffer type instead of out
- use internal signal to copy the data
 

buffer is probably a bad idea, it contaminates a design forcing the use of buffer everywhere as the LRM used to (pre-2008) state that buffer can only connect to buffer. I do know they loosened the constraints for connecting out in 2008 but not sure if it also applied to buffer with out.
 
buffer is probably a bad idea
Click to expand...
I know the said restriction of buffer ports (that they can be only connected to buffer up to the top level) from text book literature. Curiously I never found a design compiler or simulator that actually implements this restriction, thus I'm used to ignore this text book suggestion.
 

Code: 
entity mmm is
port (
  a,b: in bit;
  c,d:out bit
);
end mmm;

architecture Behavioral of mmm is
  -- option 1: "cBuf" declared as a signal
  -- (not shown)
begin
  process (a,b)
    -- option2: "cBuf" declared as a variable
    variable cBuf : bit;
  begin
    cBuf := a and b; -- evaluation and assignment cBuf is now (a and b)
    c <= cBuf; -- evaluation.  c will get the value cBuf.  However the actual assignment occurs at the end of the process.
    d <= cBuf or b; -- evaluation.  d will get the value (cBuf and b).  However the actual assignment occurs at the end of the process.
  end process; -- assignment.  at this point c is cBuf.  d is now (cBuf and b)
end Behavioral;

This avoids this logic:
Code: 
  c <= a and b;
  d <= (a and b) or b;
The issue with duplicating code is that it becomes hard to maintain. When a common sub-expression has a specific meaning, I will give it a name. Either with a variable or with a signal as required by the language. This becomes more useful when the duplicated logic is spread across the design, or not an obvious duplicate.

I read that inside the "process" statement in VHDL the commands are executed sequentially
Click to expand...
In addition to the semantics of VHDL before the 2008 standard, you also might not understand how "<=" works. This works by evaluating each statement. However the actual assignment does not happen until all lines in all triggered processes have been evaluated. VHDL also enforces ":=" for variables, where the assignment occurs at the instant of evaluation, but variables cannot be used between processes. These two features allow processes in VHDL to be processed in any order or in parallel. Only shared variables cause issues, but these normally are not used in synthesizable code (except when the tool vendor has a specific use-case).
 

Back when I used to use VHDL (a lot) one company we ran into this problem because some brainiac decided all the designs would use buffer so the outputs could be read in the architecture. Well that brilliant move cost the project money when we had to convert the entire ASIC from buffer to out so we could use the IP we bought. At least back then Modelsim (from Modeltech remember the Rhino?, not Mentor) used to adhere to the letter of the LRM, which meant there were restrictions on connecting out and buffer. Of course this was back in '95
 

vGoodtimes said:
In addition to the semantics of VHDL before the 2008 standard, you also might not understand how "<=" works. This works by evaluating each statement. However the actual assignment does not happen until all lines in all triggered processes have been evaluated.
Click to expand...

to be a pedant, it is when a process suspends (by hitting a wait or completing all lines after an event from the sensitivity list). hence why it is a critical warning when you have a process with no sensitivity lists and no wait statements as it will loop forever in 0 time.
 

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