LatticeSemiconductor
Member level 2
Hello, could someone explain me what is going on in my simulation? I have assigned a clock signal that drives some logic, cnt and sig1. This clock signal i assigned to another signal, which i use to drive sig2. I expect sig1 and sig2 beeing exactly the same, but the simulator seems to add a delta-time to it??
here is the code:
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here is the code:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity e1 is end entity ; -- e1 architecture arch_e1 of e1 is -- ------------------------------------------------------------------------------------------------- -- constants -- ------------------------------------------------------------------------------------------------- constant ctCLK1 : time := real(500_000 / 125) * 1 ps; --! 125MHz half period -- ------------------------------------------------------------------------------------------------- -- signals -- ------------------------------------------------------------------------------------------------- signal RST : std_logic:='1'; signal sig1 : std_logic; signal sig2 : std_logic; signal CLK2 : std_logic; signal CLK1 : std_logic:='0'; signal CNT : unsigned(5 downto 0) ; begin RST <= '0' after 100 ns; CLK1 <= not CLK1 after ctCLK1; CLK2 <= CLK1; orange : process( CLK1 ) begin if rising_edge (CLK1) then sig1 <= std_logic (CNT(CNT'length-1)); end if ; end process ; -- orange green : process( CLK2 ) begin if rising_edge (CLK2) then sig2 <= std_logic (CNT(CNT'length-1)); end if ; end process ; -- green counter : process( CLK1 ) begin if rising_edge (CLK1) then CNT <= CNT + 1; end if ; if RST = '1' then CNT <= (others => '0'); end if ; end process ; -- counter end architecture ; -- arch
P.S.: that image is very small, but you can click on it to expand it.