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[SOLVED] simulation strange behaviour of clock signals

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LatticeSemiconductor

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Hello, could someone explain me what is going on in my simulation? I have assigned a clock signal that drives some logic, cnt and sig1. This clock signal i assigned to another signal, which i use to drive sig2. I expect sig1 and sig2 beeing exactly the same, but the simulator seems to add a delta-time to it??

here is the code:

Code VHDL - [expand]
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library ieee;                     
   use ieee.std_logic_1164.all;  
   use ieee.numeric_std.all;      
 
entity e1 is
end entity ; -- e1
 
architecture arch_e1 of e1 is
 
-- -------------------------------------------------------------------------------------------------
-- constants
-- -------------------------------------------------------------------------------------------------
constant ctCLK1 : time := real(500_000 / 125) * 1 ps; --! 125MHz half period
-- -------------------------------------------------------------------------------------------------
-- signals
-- -------------------------------------------------------------------------------------------------
signal RST  : std_logic:='1'; 
signal sig1 : std_logic;
signal sig2 : std_logic;
signal CLK2 : std_logic;
signal CLK1 : std_logic:='0';
signal CNT  : unsigned(5 downto 0) ;
 
begin
 
   RST <= '0' after 100 ns;
 
   CLK1 <= not CLK1 after ctCLK1;
   
   CLK2 <= CLK1;
 
   orange : process( CLK1 )
   begin
      if rising_edge (CLK1) then
         sig1 <= std_logic (CNT(CNT'length-1));
      end if ;
   end process ; -- orange
 
   green : process( CLK2 )
   begin
      if rising_edge (CLK2) then
         sig2 <= std_logic (CNT(CNT'length-1));
      end if ;
   end process ; -- green
 
   counter : process( CLK1 )
   begin
      if rising_edge (CLK1) then
         CNT <= CNT + 1;
      end if ;
      if RST = '1' then
         CNT <= (others => '0');
      end if ;
   end process ; -- counter
 
end architecture ; -- arch



simulation.png

P.S.: that image is very small, but you can click on it to expand it.
 

Hello, could someone explain me what is going on in my simulation? I have assigned a clock signal that drives some logic, cnt and sig1. This clock signal i assigned to another signal, which i use to drive sig2. I expect sig1 and sig2 beeing exactly the same, but the simulator seems to add a delta-time to it??

CLK2 will occur one delta delay after CLK1 because of this assignment...
CLK2 <= CLK1;

Sig2 will occur one delta delay after Sig1 because the process that creates Sig1 responds to CLK1; the process that creates Sig2 responds to CLK2.

Get rid of the signal CLK2 and use CLK1 throughout.

Kevin Jennings
 

CLK2 will occur one delta delay after CLK1 because of this assignment...
CLK2 <= CLK1;

Kevin Jennings

Yes, that is what i can see on the simulator. But is it expected to behave this way? I assume CLK2 <= CLK1 will be synthesized into one common signal name, right? This should not take one delta time, even in simulation!
 

Yes, that is what i can see on the simulator. But is it expected to behave this way? I assume CLK2 <= CLK1 will be synthesized into one common signal name, right? This should not take one delta time, even in simulation!

This is how VHDL works, not necessarily how it will work in reality. This is the danger of renaming clocks inside your design. Also not that a port map counts as a signal assignment incuring a 1 delta penalty. But because you usually clock everything inside a single entity off the same clock signal, you dont see any issues.
 
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