regarding gate length and technology node

hi

In 130nm technology, the design of transistor with gate length below 130nm is not allowed, but, in few lower technologies like 45nm, gate lenth below 45nm is allowed. what is the relation between technology node and gate length?

On its face, 1:1. Exceptions are at the discretion of the
foundry. I have seen some use of sub-minimum FETs
even at the 0.5um node. It's all a negotiation.

dick_freebird said:

On its face, 1:1. Exceptions are at the discretion of the
foundry. I have seen some use of sub-minimum FETs
even at the 0.5um node. It's all a negotiation.

Click to expand...

I am sorry. I did not get you. could you please elaborate on this?

actually, i am a fresher pursuing custom layout design course. i did very basic layouts of standard cells in TSMC130 where i found the mosfet's length is 130nm and above. we were told that min length of the transistor is equal to the technology node(130nm here). but later, we switched to layout designing of analog schematics in GPDK45 where i have found the MOSFET'S length is below the technology node(45nm).

on what basis does this differ?

Maybe it's Ldrawn vs Leffective. Maybe it's a rules "push"
that got blessed after the process flow was named (based
on original plan). You can always draw an arbitrary L, the
question is whether or how long it will work out as thought.
As one example, in RF ICs you may see special devices like
a zero-VT FET allowed to run at Lmin-0.1u because their
application does not apply the same reliability-limiting stress
that the "normal" (digital, most likely, or general purpose)
FETs must withstand - RF is ground referred, periodically
reversing in switch applications where zero-VT helps a lot
(in an amplifier, more care must be taken because the biasing
may be not-that-unlike an analog (Class A) or digital (Class E)
application.

In any case, many possibilities - to the point that you are
asking the wrong end of the horse for wisdom.

An interesting article that should answer your question

https://semiaccurate.com/2014/08/11/intel-talks-14nm-process/

A distinguished article, unfortunately it doesn't really hit the question.