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Which VHDL construct is better for clock detection

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garvind25

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Hi,

As I know clock can be detected in VHDL through the following constructs:
  • clock’event and clock =’1’
  • rising_edge(clock)
I was going through a text book where it was mentioned that the second option is better as it detects true edge ie. for the first case, if there is a transition from ‘X’ to ‘1’ then also an edge detection will take place. I am assuming std_logic_1164 dataset.
My query is if this is true. Also, I was wondering if the second way (rising_edge) will detect an edge if there is a transition from ‘X’ to ‘1’.

Thanks,

Arvind Gupta.
 

no the edge will be detected just from low to high transition
 

The first construct as a general clock event trigger do not cover all conditions that you probably would want to detect, such as 0 to 'H'. The Second construct seems more intuitive.
 

Counterquestion, in which situation do you expect a transition from 'X' to '1'?

Obviously this is pure simulation question and hasn't much to do with FPGA design. But presumed we are talking about simulation, do you have a problem where the difference matters?
 

The rising_edge function was only standardized in the '93 revision of the language, and so many examples and engineers have stuck with the old "unsafe" form.

Imo, the function is more readable. In reality they pretty much do the same thing.
 

TrickyDicky said:
The rising_edge function was only standardized in the '93 revision of the language
Click to expand...
People who were not even born when the standard was revised, have now graduated from college. I guess not all parts of the world change so lickety-split. Check out some of the top headlines from 1993, they don't seem that much different from today. https://www.thepeoplehistory.com/1993.html
 

in all fairness, there is a massive lag between new language features and adoption by sysnthesis tool vendors.

People still use Verilog, despite SystemVerilog's decade of existence. (IEEE 1800-2005)

There was a version of Vivado that didn't recognize "group" as a reserved word for VHDL. Tool vendors are a large part of why we can't have nice things.
 

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