Gpanos
Newbie level 1
Hi all,
I've recently been trying to write [in Verilog] generic modules that will work as "wrappers" on top of other modules.
e.g. a serial interface module that could contain a basic math module like an adder, multiplier or shift/roll etc.
So, instead of creating a new module for each of them (e.g. serial_adder, serial_multiplier etc),
I was thinking of passing the basic module as a parameter to the generic module (@ instantiation).
I think the following example illustrates the idea (here, the generic module is a register for recursive additions, multiplications etc).
This code does not work however, it gives errors like "Identifier 'Adder' has not been declared yet".
My Question: What is the proper way to do this ? or is it not possible at all ?
[Note that I'm new to Verilog, so please excuse if there is something obvious I don't see]
All answers highly appreciated!
I've recently been trying to write [in Verilog] generic modules that will work as "wrappers" on top of other modules.
e.g. a serial interface module that could contain a basic math module like an adder, multiplier or shift/roll etc.
So, instead of creating a new module for each of them (e.g. serial_adder, serial_multiplier etc),
I was thinking of passing the basic module as a parameter to the generic module (@ instantiation).
I think the following example illustrates the idea (here, the generic module is a register for recursive additions, multiplications etc).
Code:
module Adder(S, A, B);
output [3:0] S;
input [3:0] A;
input [3:0] B;
assign S = A + B;
endmodule
module Serial_calc #(parameter aModule = Adder) (Result, D, CLK);
output reg [3:0] S;
input [3:0] D;
input CLK;
wire [3:0] S_temp;
aModule M0(S_temp, S, D);
always @(posedge CLK) begin
S <= S_temp;
end
endmodule
//--- Instantiation ---
Serial_Calc #(Adder) M0(Result0, D, CLK0);
Serial_Calc #(Multiplier) M1(Result1, D, CLK1);This code does not work however, it gives errors like "Identifier 'Adder' has not been declared yet".
My Question: What is the proper way to do this ? or is it not possible at all ?
[Note that I'm new to Verilog, so please excuse if there is something obvious I don't see]
All answers highly appreciated!