VHDL code for Complex matrix multiplication

how to do matrix multiplication using VHDL if the entries in the matrix are complex numbers (a+jb) ?
is there is any synthesizable package for complex matrices or any different procedure to be followed for that..?

the math_real package defines the complex type - and arithmatic for them.
However, this is not a synthesisable package and is for modelling only.

Complex numbers are nothing special. It is just a simple matrix operation:

(a+jb)(c + jd) = (ac - bd) + j(ad + bc)

So all you need are 4 mults and 3 adders.

What is the size of the matrices?
What is the speed requirement?

You must first decide if you want a parallel or sequential solution. A parallel solution with large matrices will consume a lot of hardware resources.

I have to multiply 4x64 and 64x4 matrices....

This is probably not feasible to complete in a single cycle. You will want to specify how often the operation needs to be performed and the resolution of the input/output. for example, do you need floating point for the wide dynamic range, or is fixed point ok. (fixed point has a decimal place as well)

saran86 said:

I have to multiply 4x64 and 64x4 matrices....

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Most likely the matrices do not 'magically' appear. Instead they arrive entry at a time, or in some other fashion. The point is that you most likely do not have a 4x64 matrix and a 64x4 matrix ready to go before you can do anything. Instead you collected the data for those matrices (and chose to do nothing) and then find yourself with the matrices.

Ignoring the time that the data is being received is usually a big mistake. For example, let's say that you receive one matrix entry per clock cycle, the 4x64 matrix first followed by the 64x4. So when you're receiving the 4x64 matrix you can't do anything except store those entries for later retrieval. Now on the clock cycle when you receive the first entry of the 64x4 matrix, you can immediately compute the output, no need to even store the 64x4 matrix data. You need only one complex multiplier to do the math and can probably compute the output result in one clock cycle depending on what part you're implementing this in and what your clock speed requirements are. On the next clock cycle, you get the next entry in the 64x4 matrix and can compute the second output. So on and so on. The last entry in the result will be available one clock cycle after the last input is received. That's a lot different problem now isn't it? Unfortunately, you haven't given any details about how the data gets in and out and I've made assumptions here that may or may not be realizable in your system. In order to give more reasonable feedback though, you'll need to provide the I/O information (or maybe you haven't considered that yourself yet...if not, then you should).

Kevin Jennings

Most likely the matrices do not 'magically' appear.

Click to expand...

Brilliant phrase.