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Formula or tools for converting LUTs to count gates

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gnudaemon

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Convert LUTs to Gates

Hi,
Is there any formula or tools to convert LUTs to Gates count. I made my design in Xilinx board XC2V1000 and XC2V3000.
Thanks a lot
 

Convert LUTs to Gates

This can be done by ISE Map tool. The report generated by MAP can give out the "equivalent gate count" for the design.
Please read the xxx.mrp file and find it.
 

Convert LUTs to Gates

Hi darylz:
Which software package ISE Map belongs to ?
I have Xilinx ISE but I can't find ISE Map.
 

Convert LUTs to Gates

https://www.deepchip.com/items/0356-05.html

Frag Virtex ASIC equivalent
gates
---------------------------------------
4-input LUT 6
4-input ROM 32
3-input LUT na
16x1 RAM 64
32x1 RAM 128
16 Shift Reg LUT 64
CLB flop 8
CLB latch 5
IOB flop 8
IOB latch 5
IOB Sync latch na
TBUF 3
Block RAM 16,384
BSCAN 48
Clk DLL 7,000
F5 MUX 3
F6 MUX 3
MUXCY 3
XORCY 3

An old document but can give rough estimates..

MAP can be found in the Process Viewer window under
Implement Design tab in XILINX ISE only..
 

Convert LUTs to Gates

Thanks,
Frankly I think I must use some tools. Estimation is not correct.
 

Re: Convert LUTs to Gates

gnudaemon said:
Thanks,
Frankly I think I must use some tools. Estimation is not correct.

as said,gate count value will be provided by the map report generated by the mapping process.
but y r u specific on this gate count value.
usually for fgpa designs v shud look for the total resource utilization interms of the LUTS and BRAMs and multipliers, iobs,flops.

plz correct, if i'm wrong.
 

Convert LUTs to Gates

I've got the number of LUTs, but were asked to calculate gates count.
I have currently got Synplicity and Xilinx ISE 6.1. Is there a way to obtain gates count from those softwares?
 

Convert LUTs to Gates

ok...as u have xilinx ise 6.1, u can obtain the gate count of ur design.
do u know how to implement the design through
syntheis--translate--mapping--place and route
using the ise 6.1.
if u know then, view the Map report.
This reports tells the total resouce utilization, and the next to that is the Gate count of ur design.
 

Convert LUTs to Gates

So far I've observed from synthesis that number of register bits are same.
Are the number of gates different between Xilinx and Altera box?
Pls give me your opinion
 

Convert LUTs to Gates

gate counts for the luts of xilinx and altera need not be the same as they differ in their architecture.
have u run the mapping process after ur synthesis?
 

Convert LUTs to Gates

what do you mean Renjith?
 

Convert LUTs to Gates

i just asked u, whether have u found the gate count for ur design?
 

Convert LUTs to Gates

No. The log file only outputs the LUTs and number of register bits for Xilinx.
If I choose to synthsize with Altera MAXII, log file gives the gates count and register bits, but not LUTs.
 

Convert LUTs to Gates

you can't give the number for gates to a LUT. it is just estimated by some experiences. according to me , a LUT in the altera's FPGA is subjected to about 17~19 gates. in this way, a SLICE in the Xilinx's FPGA to 34~38 gates.
 

Re: Convert LUTs to Gates

gnudaemon said:
Hi darylz:
Which software package ISE Map belongs to ?
I have Xilinx ISE but I can't find ISE Map.

Map is one of the tools included in ISE development system.
below is quoted from the my map report:

Number of bonded IOBs: 397 out of 416 95%
IOB Flip Flops: 479
IOB Master Pads: 2
IOB Slave Pads: 2
Number of PPC405s: 0 out of 2 0%
Number of GTIPADs: 16 out of 24 66%
Number of GTOPADs: 16 out of 24 66%
Number of Block RAMs: 158 out of 192 82%
Number of GCLKs: 8 out of 16 50%
Number of DCMs: 3 out of 8 37%
Number of GTs: 8 out of 12 66%
Number of GT10s: 0 out of 0 0%

Total equivalent gate count for design: 11,656,098
Additional JTAG gate count for IOBs: 19,056
 

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