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Frag Virtex ASIC equivalent
gates
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4-input LUT 6
4-input ROM 32
3-input LUT na
16x1 RAM 64
32x1 RAM 128
16 Shift Reg LUT 64
CLB flop 8
CLB latch 5
IOB flop 8
IOB latch 5
IOB Sync latch na
TBUF 3
Block RAM 16,384
BSCAN 48
Clk DLL 7,000
F5 MUX 3
F6 MUX 3
MUXCY 3
XORCY 3
gnudaemon said:Thanks,
Frankly I think I must use some tools. Estimation is not correct.
gnudaemon said:Hi darylz:
Which software package ISE Map belongs to ?
I have Xilinx ISE but I can't find ISE Map.
Number of bonded IOBs: 397 out of 416 95%
IOB Flip Flops: 479
IOB Master Pads: 2
IOB Slave Pads: 2
Number of PPC405s: 0 out of 2 0%
Number of GTIPADs: 16 out of 24 66%
Number of GTOPADs: 16 out of 24 66%
Number of Block RAMs: 158 out of 192 82%
Number of GCLKs: 8 out of 16 50%
Number of DCMs: 3 out of 8 37%
Number of GTs: 8 out of 12 66%
Number of GT10s: 0 out of 0 0%
Total equivalent gate count for design: 11,656,098
Additional JTAG gate count for IOBs: 19,056