Johnny_freeman78
Newbie level 1
I need some help getting started with writing the following two sort .sv file. Can someone help?
(a) sortEight.sv Write a module sortEight, which accepts eight signed values and returns eight signed values sorted from least to greatest. You should submit one file for this problem called “sortEight.sv”. Any additional modules should be included in the file. You should not change the interface provided below. (Hint: Start by constructing a sortTwo module and then drawing a block diagram for a parallel bubble sort).
(b) firstOne.sv Write a module firstOne.sv, which accepts a 16 bit string and returns a 16 bits string that is one-hot. The output “B” should indicate the position of the “left- most-one” in the input. For example, 11111011 → 10000000 ; 00001011 → 00001000. Note that we consider the MSB to be the left most position. Any additional modules should be included in the file. You should not change the interface provided below. (Hint: Start by thinking about our ripple carry adder, which evaluates an individual bit slice. Each slice in this case needs to know if anyone to the left has been one. Think about building a local version. Alternatively, you might be interested in using don’t care conditions in a priority case statement).
(a) sortEight.sv Write a module sortEight, which accepts eight signed values and returns eight signed values sorted from least to greatest. You should submit one file for this problem called “sortEight.sv”. Any additional modules should be included in the file. You should not change the interface provided below. (Hint: Start by constructing a sortTwo module and then drawing a block diagram for a parallel bubble sort).
Code Verilog - [expand]
(b) firstOne.sv Write a module firstOne.sv, which accepts a 16 bit string and returns a 16 bits string that is one-hot. The output “B” should indicate the position of the “left- most-one” in the input. For example, 11111011 → 10000000 ; 00001011 → 00001000. Note that we consider the MSB to be the left most position. Any additional modules should be included in the file. You should not change the interface provided below. (Hint: Start by thinking about our ripple carry adder, which evaluates an individual bit slice. Each slice in this case needs to know if anyone to the left has been one. Think about building a local version. Alternatively, you might be interested in using don’t care conditions in a priority case statement).
Code Verilog - [expand]
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