synq
Member level 2
hi........
could any one help me to figure out the relation between 50% duty cycle and speed factor in FPGA.?
any links or documents.?
How far I need to keep the 50% duty cycle as Iam planning to boost the frequency from 20Mhz to 300Mhz.?
could any one help me to figure out the relation between 50% duty cycle and speed factor in FPGA.?
any links or documents.?
How far I need to keep the 50% duty cycle as Iam planning to boost the frequency from 20Mhz to 300Mhz.?