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problem in system verilog program

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Ahmed Hisham

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Code: 
module aaa(input logic a,b,c,output logic y);
	assign y=~a&~b&~c | a&~b&~c | a&~b&c;
endmodule

i am using Quartus for simultion at the begining of the creation of the project i chosed verilog
as there is no for system verilog

now this error is given to me for the code a

Error (10161): Verilog HDL error at aaa.v(2): object "logic" is not declared
 

You have two options:
1> Use a compiler and simulator that supports System Verilog constructs.
2> If not<1>, then change your 'module aaa' to Verilog

Converting it to Verilog or for the matter of fact writing a new Verilog module seems pretty easy from the logic you have provided. That is your task!

So this SV cheatsheet might help you in case you want to go with option <2>.
https://www.cl.cam.ac.uk/teaching/1112/ECAD+Arch/files/SystemVerilogCheatSheet.pdf
 

does the later versions of Quartus support system verilog
 

Try using the file extension .sv instead. If Quartus simulator is anything like Vivado's it will automatically use system verilog if it sees yhat extension.
 

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