Using Bitwise XOR or XOR_REDUCE ???

Hello,

I have two vectors A and B that are defined as STD_LOGIC_VECTOR in VHDL. I would like to XOR each pair of correspoing bits from A and B (a0,b0 a1,b1, ...) and ONLY have ONE output at the end to use this output as a flag. I am confused to use XOR_REDUCE function or performing a BITWISE XOR operation?? As I know, the XOR_REDUCE will perform xor on all bits of each individual vector and BITWISE operation will have a VECTOR at its output nor ONE output !!

Any kid help is cordially appreciated

Regards,

Assuming you're looking for a single output bit (to show that only 1 bit is set in either vector), just do the xor_reduce function on each and then xor the results:

op <= xor_reduce(a) xor xor_reduce(b);

I think understanding the question in paramount

Do you want to
or do you want to
Or do you want some sort of hybrid like the following?

msdarvishi said:

Hello,

I have two vectors A and B that are defined as STD_LOGIC_VECTOR in VHDL. I would like to XOR each pair of correspoing bits from A and B (a0,b0 a1,b1, ...) and ONLY have ONE output at the end to use this output as a flag.

Click to expand...

You don't say how you want to convert the vector to a single output, but I'm assuming that after you've xor'ed the bits in each vector to produce a new vector that you want to 'or' those bits together. So you would have

Gazouta <= or_reduce(a xor b);

In VHDL-2008, you can also say
Gazouta <= or(a xor b);

Kevin Jennings

TrickyDicky said:

Assuming you're looking for a single output bit (to show that only 1 bit is set in either vector), just do the xor_reduce function on each and then xor the results:

op <= xor_reduce(a) xor xor_reduce(b);

Click to expand...

I think you did not understand the question clearly. I have a vector for input A and a vector for input B. I want to bitwise XOR each element of vector A with its corresponding element in vector B (for example a0 xor b0 , a1 xor b1 , ... ), but finally I ONLY need ONE bit output as a flag signal to enable another part of my design.
As I know, the xor_reduce function will do an XOR for all elements of vector A and separatrly for the elements of vector B separately which is not the objective that I follow.

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wesleytaylor said:

I think understanding the question in paramount

Do you want to

Code:

a(1) XOR b(1)

or do you want to

Code:

a(1) XOR a(2) ?

Or do you want some sort of hybrid like the following?

Code:

for I in 1 to a'length
  temp(I) <= a(I) XOR b(I);
end loop;

temp1 <= xor_reduce(temp);

Click to expand...

The 3rd assumption that you made is my objective !! But I think finally I have to do or_reduce of the temp(I) vector instead of doing xor_reduce on that ! Because the temp signal will be used as a flag in order to enable another part of my design.

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K-J said:

You don't say how you want to convert the vector to a single output, but I'm assuming that after you've xor'ed the bits in each vector to produce a new vector that you want to 'or' those bits together. So you would have

Gazouta <= or_reduce(a xor b);

In VHDL-2008, you can also say
Gazouta <= or(a xor b);

Kevin Jennings

Click to expand...

I agree with you assumption. The output vector of the bitwise XOR on two vectors A,B is a vector of flag signals. Finally each of these flags that raises would be enough to raise my final output flag signa. So, the outputs must be "or" or "or_reduce" in order to provide a single output bit.

Do you agree??

I have a vector for input A and a vector for input B. I want to bitwise XOR each element of vector A with its corresponding element in vector B (for example a0 xor b0 , a1 xor b1 , ... ), but finally I ONLY need ONE bit output as a flag signal to enable another part of my design.

Click to expand...

You forgot to mention (or may be didn't even think about) the intended relation between the vector that is generated by bitwise XOR of A and B and the single output bit. It may be a REDUCE_OR, as guessed by K-J or anything else, e.g. REDUCE_XOR, as assumed by TrickyDicky.

"enable another part of my design" can mean anything.

FvM said:

You forgot to mention (or may be didn't even think about) the intended relation between the vector that is generated by bitwise XOR of A and B and the single output bit. It may be a REDUCE_OR, as guessed by K-J or anything else, e.g. REDUCE_XOR, as assumed by TrickyDicky.

"enable another part of my design" can mean anything.

Click to expand...

I have 2 input vectors A , B.
I want to bitwise XOR each pair of correspinding bits from vector A , B (a0 with b0 , a1 with b1, ...). It it like a bitwise comparator that checks only equality of two vectors.
Then any of the outputs of bitwise XOR function that is '1' would be enough to assert a flag signal...! That's all !
I think with this clarification I think the solution provided by K-J will satisfy the objective. Do you agree??

Yes, K-J's solution is correct.

There are alternative solutions in this case:

Concurrent:

Sequential: