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Xilinx Aurora vs Chip2Chip

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shaiko

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Hello,

Can someone please highlight the differences between Xilinx's Aurora and Chip2Chip protocols?

I did some reading on the subject and they seem to be almost identical...
 

Aurora is transceiver based, chip to chip uses iserdes oserdes in the selectmap i/o.
 
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Thanks.

1, But isn't a transceiver the same thing as a SERDES ?
2. Any differences in the protocol itself?
 

1. No, the transceivers are CML hard IP transmit and receive multi-gigabit serial links (GTX/GTH/GTP, etc). SERDES is just a serial/deseralizer. Both the C2C and the transceivers use SERDES but they are different hard IP. The ISERDES/OSERDES blocks are in the selectmap I/O.

2. Chip-to-chip uses AXI as its protocol and is implemented as a source synchronous interface. The transceivers uses 8b10b or 64b66b encoding to achieve both DC balancing and clock recovery (I'm pretty sure you can use the coregenerator to produce a wrapper that interfaces the transceivers to AXI).

For 7 Series parts.
Refer to the "SelectIO Logic Resource" section of UG471 and UG476 for information on the GTX/GTH transceivers.
 
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2. Chip-to-chip uses AXI as its protocol and is implemented as a source synchronous interface.
Isn't Aurora also source synchronous?
Doesn't Aurora also use the AXI like C2C?
 

Aurora is not source synchronous, it uses the CML transceivers and recovers the transmit clock at the receiver from the data, hence the need for 8b10b or 64b/66b encoding to ensure enough transitions occur to allow clock recovery and keep the DC level constant.

For 3.125Gbps aurora you only need a single differential pair (2 wires). For a source synchronous serial interface you need at least a clock and a data connection (if differential then that means four wires).
 
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Aurora is not source synchronous, it uses the CML transceivers and recovers the transmit clock at the receiver from the data, hence the need for 8b10b or 64b/66b encoding to ensure enough transitions occur to allow clock recovery and keep the DC level constant.

So by "Source Synchronous" you mean that a dedicated clock signal traves from master to slave?

Because I see that the C2C also makes use of 8B/10B...
Why does it need it if not for clock recovery? Why can't it transmit raw unscrambled data?
 

So by "Source Synchronous" you mean that a dedicated clock signal traves from master to slave?
yes

Because I see that the C2C also makes use of 8B/10B...
Why does it need it if not for clock recovery? Why can't it transmit raw unscrambled data?
Guessing based on other benefits of encoding the data....besidss clock recovery 8b10b means you have 4x the number of symbols, and 8b10b was designed such that any single bit flip produces an invalid symbol (instant error detection). Also there are extra K-codes for things like idle, start, stop, etc. Whick are mighty handy for packet based protocols such as AXI.

I'm somewhat assuming that it was convienent to use 8b10b than create something new. I'd have to look into it to determine how accurate my guess is.

- - - Updated - - -

It is interesting to note that you can use the Aurora PHY for the Chip2Chip interface...see Figure 1-1 and Figure 3-2 in PG067. I guess taking advantage of the transceivers to implement a version of the Chip2Chip interface is one of the options besides using the SelectIO PHY. I now see that the 8b10b references you are seeing are due to the Aurora core.
 
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So when will you choose to use one over the other?
 

So when will you choose to use one over the other?

You mean between the Chip2chip with GTX or the SelectIO?

It depends on the bandwidth requirements of the interface. It takes more pins to have an equivalent bandwidth for SelectIO compared to the GTX/GTH.
 

You mean between the Chip2chip with GTX or the SelectIO?
No...
I meant between using C2C vs using Aurora...
 

Well what I stated in #10 depends on your requirements (both bandwidth and address architecture). Aurora with bonded channels will have significantly more bandwidth with way less pins than a C2C using SelectIO. If you use C2C with Aurora PHY then you're basically just avoiding having to build a non-streaming interface for Aurora's streaming AXI yourself. If you have latency requirements the C2C using SelectIO has the minimum latency of the two PHY.

You should probably read PG067 as all of this is from there. I actually had to browse that document (again) as I haven't looked at it for quite some time.
 
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