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Xilinx Remote FPGA bitstream updating

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flote21

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Hi guys!

I am planing to do a project with Xilinx FPGA and I would like to know which XIlinx FPGA family supports remote flash updating.

The plan is to program the FPGA with a default .mcs file via JTAG only once and update the bitstream of the flash memory programming in the FPGA and IP module for flashing the flash with the new bitstream later.

Anybody knows if this is possible to do it with Xilinx FPGAs??? Is there any application note respecting to this?

Thanks!
 

Hi,

something like XAPP951?

Klaus
 

Yes,

But you need the JTAG Xilinx Cable to programm the FPGA. The idea is that the PC is transferring via ETH the bitstream and the FPGA programm the flash memory on the fly...
 

You don't program the FPGA with the .mcs file, it is the flash prom you program with it. You need the .bit to program the FPGA (no prom).

XAPP951 shows you that you can program the FPGA (.bit) with the JTAG port and the flash with a SPI port. For your application, you can program the FPGA with the JTAG port and once the FPGA is in user mode you can use whatever interface to program the flash on the fly through the SPI port. You just need to be sure that the spi configuration pins are available in user mode.
 

I would suggest you to check out the board spec of your target device and specially look into the flash memory details. Investigate the various ways (if possible) to program the flash chip provided.
Most FPGA boards will only have the Eth PHY chip. But you need to provide a MAC core to Rx/Tx data through it. So where do you want to place a MAC core needs to be considered! That would be one part.
The other part would be to transmit the bit file from the Eth MAC to your SPI Flash.
 

The idea is to use this Xilinx Spartan 3A DSP: 3SD1800A-FG676 FPGA. However I have checking the next app note:

https://www.xilinx.com/support/documentation/application_notes/xapp468.pdf

And it says that I have to implement a Picoblaze inside to program the flash.
And I would like to avoid the implementation of the Picoblaze. Is it possible to do it without any Picoblaze?

Thanks
 

And it says that I have to implement a Picoblaze inside to program the flash.
Click to expand...
Certainly it does not say you "have to". The particular application note suggests a way to update the flash from embedded processor. Of course you can write pure HDL code that does the same.

I have a HDL bootloader component in some Altera designs that among other things parses a hex file received at an UART interface and writes it to FPGA configuration flash.

Using embedded processor cores for slow sequential activities is a matter of optimal resource utilization and coding ease. Above a certain level of design complexity it's probably reasonable. You'll find it often used for functions like ethernet or USB stacks implemented in a FPGA. Programming a SPI flash is straightforward and can be well done with hardwired logic.
 

FvM said:
Certainly it does not say you "have to". The particular application note suggests a way to update the flash from embedded processor. Of course you can write pure HDL code that does the same.

I have a HDL bootloader component in some Altera designs that among other things parses a hex file received at an UART interface and writes it to FPGA configuration flash.

Using embedded processor cores for slow sequential activities is a matter of optimal resource utilization and coding ease. Above a certain level of design complexity it's probably reasonable. You'll find it often used for functions like ethernet or USB stacks implemented in a FPGA. Programming a SPI flash is straightforward and can be well done with hardwired logic.
Click to expand...

Hi FVM!!

You say that you have implemented HDL bootloader configuration in some altera FPGAS? is it possible to have a look to your code?

On the other hand I have been doing a research and Xilinx recommend to implement a Picoblaze to do the bootloader in a Spartan 3A...I don'y know if anyone here has been able to do it without the picoblaze....

Thanks!
 

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