niteshtripathi
Member level 3
Hello everyone, I have to design a module which has of three inputs clk,inc and dec respectively.
first case,when both inc and dec are zero the output is simply the clkfreq/2. In order to achieve this i am using T Flipflop (where input t=1)
second case,At rising edge of inc if flipflop output is at zero then t flipflop output gets high in next clk cycle and after that it should remain in low state in next two clk cycle.
third case, At rising edge of inc if flipflop output is at high then t flipflop output gets low in next clk cycle and after that it should remain in low state in next two clk cycle.
Please suggest the logic
see the attached file
first case,when both inc and dec are zero the output is simply the clkfreq/2. In order to achieve this i am using T Flipflop (where input t=1)
second case,At rising edge of inc if flipflop output is at zero then t flipflop output gets high in next clk cycle and after that it should remain in low state in next two clk cycle.
third case, At rising edge of inc if flipflop output is at high then t flipflop output gets low in next clk cycle and after that it should remain in low state in next two clk cycle.
Please suggest the logic
see the attached file