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occasional power on wrong state of Xilinx virtex II FPGA

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xuexucheng

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Hello everyone,
I met a very wired problem. I use a Xilinx virtex II FPGA(x2v3000).
There is a internal signal that should be 0 when power on, but when power on this signal occasional is 1 for a clock cycle. This could happen about 1 time every 20 times power on. The below is the FPGA edtor result. The D terminal of the flipflop is globle 1, the ck is globle clock, the SRLOW terminal is controlled by other signals. And the reset type is synchronous. I connect the internal signal to IOs to monitor using osciloscope. I fine the SRLOW is 0, but there maybe 1 at the output of the flipflop. I also put the code in different FPGA board. The result is same. This is a very hard problem. Any reply is welcome. Thanks in advance.

IMG_20160114_172453.jpg
 

The typical source of intermittent problems as you have described is a timing error. Probably the clock is coming along at a time that you're not expecting and is violating the setup or hold time of the flip flop and is causing a 1 to be stored.

The bigger question though is why you have a design that would care exactly which state a flip flop is in immediately after power on. Good design practice is that one would design in a reset mechanism that insures that things are in the proper state and then synchronously remove the reset to allow the design to operate normally. It appears that either you don't have such a design, or perhaps you were just curious and decided to look at this particular flip flop after power on.

Kevin Jennings
 
Last edited:

Most FPGAs have power on reset to known state, Virtex II surely has. But in case a clock is already applied during power-on reset, you may need to implement a dedicated asynchronous reset which is released synchronous to the clock, otherwise the POR end may involve a hold time violation.
 
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Your clock is a global, but that doesn't say how it is generated, is it the output of a DCM? If so then the reset you are generating better be held until after the DCM says it's locked. The DCM clock outputs aren't stable and can cause setup/hold violations on FFs in the device if they are not held in reset. Also you should use the recommendations already given on releasing the reset.
 
FvM said:
Most FPGAs have power on reset to known state, Virtex II surely has. But in case a clock is already applied during power-on reset, you may need to implement a dedicated asynchronous reset which is released synchronous to the clock, otherwise the POR end may involve a hold time violation.
Click to expand...
FvM is indeed a giant! So brilliant!

you may need to implement a dedicated asynchronous reset which is released synchronous to the clock
------ I can implement that, however, I do not want to add the reset circuit. You know the reset circuit need additional considerations. I think that the power on reset by Xilinx FPGA is simple and easy to use.
But in case a clock is already applied during power-on reset,
------ You mean if there is no clock during power-on reset, then there will be no problem? Which user guide or application note describe this?
otherwise the POR end may involve a hold time violation.
------ Coud you explain this in much detail? Thank you. Which user guide or application note describe this?

Thank you again!
 

If you want to use the POR that is generated after configuration (a bad design practice to rely on that), then you need to ensure that there no clocks running prior to configuration and there are no DCMs used. The clock to the FPGA should be enabled without glitches, otherwise you'll end up with probably timing violations.
 

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A straightforward solution is a power supervisory and reset controller driving a dedicated FPGA reset input. Reset timing should be adjusted so that all input clocks and PLL outputs are stable before the reset is released. FPGA internally, the asynchronous reset must be synchronously released, you probably need separate reset synchronizers for each clock domain.

Design of reset synchronizers is described in many vendor application notes, e.g. in the Quartus software handbook

resetsync.png

In case no external reset is available, an internal reset counter can work as a replacement, with somewhat reduced reliability. It can be e.g. started after the PLL signals locked state.
 

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Thank you for your replys. I've learned so much from you on the reset stuff.
But the crital question is that is my question cased by the reset problem?
The D terminal of the flipflop is globle 1, the ck is globle clock, the SRLOW terminal(the reset terminal, the reset type is synchronous) is controlled by other signals. I connect the internal signal to IOs to monitor using osciloscope. I fine the SRLOW is 1(i.e. the synchronous reset is active), but there maybe 1 at the output of the flipflop for a clock cycle. You know there is no condition that makes the output to become 1, because the SRLOW is 1(active)!
Thank you.
 

The only explanation I can see is a timing violation between "CK" and "SR". Can you describe the logic that drives "SR"?
Can "SR" be guaranteed to be '1' when the first "CK" transition occurs?

Have you measured "CK" and "SR" at the same time with the oscilloscope?
 
std_match said:
The only explanation I can see is a timing violation between "CK" and "SR". Can you describe the logic that drives "SR"?
Can "SR" be guaranteed to be '1' when the first "CK" transition occurs?

Have you measured "CK" and "SR" at the same time with the oscilloscope?
Click to expand...

I have measured "CK" and "SR" at the same time with the oscilloscope, the strange thing is that the SR is always '1' when the registor output the 1 clock cycle high level.
any idea is welcome.
 

The phenomenon is strange. we can not explain it use the D flipflop principle. Is this a known issue of Virtex II FPGA?
Could any nice guy explain why?
Thanks again.
 

std_match said:
Please show the involved source code.
Click to expand...

Code VHDL - [expand]
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signal soft_start : std_logic := '0';
process(clk)
begin
    if rising_edge(clk) then
        if s_start='1' and s_start_cmd=b"111" then
            soft_start<='1';
            soft_stop<='0';
        elsif s_stop='1' and s_stop_cmd=b"111" then
            soft_start<='0';
            soft_stop<='1';        
        else
            soft_start<='0';
            soft_stop<='0';        
        end if;
    end if;
end process;


The above is the code. The phenomenon is the 'soft_start' occasional become '1' for a clock cycle after power up. (In fact, I connect the 'soft_start' to a FPGA pin. Then measure it using osciloscope. First the 'soft_start' is high level becasue the pullup of the pin. Then the 'soft_start' become low level because of the init value '0'. However, occasional, about 200ns after the low level, the 'soft_start' become high level for a clock cycle.) So, the phenomenon is not afer power up, but about 200ns after the low level.
The picture in the first message is from the Xilinx FPGA editor. The CR signal is controlled by the signal s_start and the signal s_start_cmd. The CR is the AND NOT operation of s_start and s_start_cmd. So I also connect s_start signal, s_start_cmd signals to the FPGA pins. Also I connect the CR(the terminal of D flipflop) signal to FPGA pin using the FPGA editor probe function. But when the 'soft_start' become high level when problem, the s_start and s_start_cmd is low level, meanwhile the CR signa is high level.
 
Last edited by a moderator:

do s_start and s_start cmd also have initial values of 0? are they async reset?
 
TrickyDicky said:
do s_start and s_start cmd also have initial values of 0? are they async reset?
Click to expand...

The s_start and s_start_cmd have value '0' using the Xilinx INIT property.
i.e. signal s_start : std_logic := '0'; signal s_start : std_logic_vector := "000";
They only have power on config values. They do not have reset pins.

The critical thing is that I have measured that when soft_start is high but s_start and s_start_cmd are all low.
 

Please show also the code for assigning values to s_start and s_start_cmd.
 

std_match said:
Please show also the code for assigning values to s_start and s_start_cmd.
Click to expand...
The code for for assigning values to s_start and s_start_cmd is too many. I think the problem is not caused by s_start and s_start_cmd, because I test them using oscilloscope. They are keep '0' when there is problem.
 

Have you tried raising the issue with your FAE or direct with Xilinx? they could look at your project for you if you wont/cant share code with us.
 

Are s_start and s_start_cmd generated by registers or combinatorial logic?
If registers, is it the same clock as for creating soft_start?
What is the clock frequency?
 

std_match said:
Are s_start and s_start_cmd generated by registers or combinatorial logic?
If registers, is it the same clock as for creating soft_start?
What is the clock frequency?
Click to expand...

s_start and s_start_cmd generated by registers. same clock as for creating soft_start. clock frequency is 100MHz. Static timing analysis is OK.
 

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