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occasional power on wrong state of Xilinx virtex II FPGA

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Until we get the project or code - there is little we can do to help
 

s_start and s_start_cmd generated by registers. same clock as for creating soft_start. clock frequency is 100MHz. Static timing analysis is OK.

Do you have any asynchronous set/reset for s_start or s_start_cmd?
 

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