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[SOLVED] MicroBlaze - Can I run an application on Vivado SDK without a board ?

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slutarius

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Hi guys,

I am new to MicroBlaze and app SDK of Vivado.

I want to write an application, say in C, to test my hardware IP which was generated from Vivado.
The hardware is an MicroBlaze with Uart IP connected via a AXI interconnect. Other component are clock and reset support, MIG to connect with DDR3 IF.

My questions:
I dont have a board now, so can I test my program on Vivado SDK without a board ?
Is there monitoring conponent to capture uart data and so on ?

It keeps saying that I need a board to run the test application. Board.png

Thanks,
 

no you are not able to run it without a board. Although you may use Mentor Graphics Modelsim or Vivado's tool to simulate the PL section of exist in your project.
 

moh.haroun said:
no you are not able to run it without a board. Although you may use Mentor Graphics Modelsim or Vivado's tool to simulate the PL section of exist in your project.
Click to expand...

Thanks for the reply.

I am OK with PL section only simulation.
For PL + PS simulation, there is no choice but Board, right ?
 

moh.haroun said:
no you are not able to run it without a board. Although you may use Mentor Graphics Modelsim or Vivado's tool to simulate the PL section of exist in your project.
Click to expand...

Why not?

In principle it should be possible to run an RTL simulation with your C-code as the test-case.
It is possible to embed your test-case/C-code within the uBlaze memory (BRAM) and the uBlaze can read it while simulating in the Vivado software. Thus you can view/debug your design in simulation even before going the bare-metal way.

I have not done such as thing with a uBlaze, but with a custom 32bit processor and have implemented on Spartan6. I always used to run RTL sim with my C-code before testing the same C-code on bare-metal (only here you need a board).

See this docu:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/ds865_microblaze_mcs.pdf
 
Is is possible in theory, but maybe not practical because of long simulation times.
The software should run for a very short time to minimize the simulation time.

It is normally better to test the hardware IP with a test bench written i a language that the simulator understands. You then have exact control of the stimuli timing and it is easy to correlate the simulator waveforms with the test code. It is also easy to inject errors in the stimuli.
 

Well std_match, I agree with you, when the test-case is small. With my C code I was *only* testing the responses of IIC slaves connected via a memory mapped AXI4Lite bus (master) which was directly connected to the uP core.
In my case, in the RTL Tb, I made the uP read from a HEX file (which contained the test-case). I could see the responses fast in my simulator.
 

dpaul said:
Why not?

In principle it should be possible to run an RTL simulation with your C-code as the test-case.
It is possible to embed your test-case/C-code within the uBlaze memory (BRAM) and the uBlaze can read it while simulating in the Vivado software. Thus you can view/debug your design in simulation even before going the bare-metal way.

I have not done such as thing with a uBlaze, but with a custom 32bit processor and have implemented on Spartan6. I always used to run RTL sim with my C-code before testing the same C-code on bare-metal (only here you need a board).

See this docu:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/ds865_microblaze_mcs.pdf
Click to expand...

Thanks for the comment.
How to compile and load the instruction code to MicroBlaze execution memory, that is what I was am looking for. The document does not say anything.
 

Give me some time to answer the above question.
 

Hi slutarius,

Following the LogiCORE IP MicroBlaze Micro Controller System v2.2, PG116 April 2, 2014, I have understood that merging the .elf file with the design is only possible after the Synthesiz Project' stage. See the flowchart on page 30, Figure 4-9: Generic Vivado Tool Flow.

This comes as a surprise to me!
I thought it would be possible somehow populate the BRAMs of a uBlaze MCS with an .elf and then run the entire design in simulation. This make debugging easy. I don't understand why Xilinx would allow to do such a thing.

Nevertheless I have opened a thread in the Xilinx forums and will wait to see their response.
 
dpaul said:
Hi slutarius,

Following the LogiCORE IP MicroBlaze Micro Controller System v2.2, PG116 April 2, 2014, I have understood that merging the .elf file with the design is only possible after the Synthesiz Project' stage. See the flowchart on page 30, Figure 4-9: Generic Vivado Tool Flow.

This comes as a surprise to me!
I thought it would be possible somehow populate the BRAMs of a uBlaze MCS with an .elf and then run the entire design in simulation. This make debugging easy. I don't understand why Xilinx would allow to do such a thing.

Nevertheless I have opened a thread in the Xilinx forums and will wait to see their response.
Click to expand...

I saw the thread. I also associate ELF to MicroBlaze and involke simulation tool. There is no issue from tool so far.
I am going to correct clock, reset on testbench to see how it works.
 

My questions:
I dont have a board now, so can I test my program on Vivado SDK without a board ?
Is there monitoring conponent to capture uart data and so on ?
Click to expand...

I have not given up and have found that it is indeed possible to run your ELF in h/w sim mode. Yes, you can test your C code on the uB, but you have to use Vivado and not SDK.

I have taken a uB MCS having a UART, 4 bit GPI and 4 bit GPO and have developed a hello_world.c around it.

In my attached SS, you can see the print() transmitting some UART chars and the dec(4) being written to the o/p LEDs.

All you have to do is to go to Tools > Associate ELF Files, and then under 'Simulation Sources' you have change the elf for the uB MCS from the default mb_bootloop_le.elf to to hello_world.elf.

Then with your top level test bench just run the simu the usual way.

Attached is the screen-shot. MB_elf_sim.jpg
 
That associate elf file dialog changes the RTL generated to load the memory array with whatever was in the elf file you put there. I'm pretty sure the elf file contents get converted first to some hex file so the memory array can be initialized in the RTL from the hex file contents (instead of the RTL using the elf file directly).

GUI users (that use only the Xilinx GUI flow) likely aren't that familiar with compiling all the RTL simulation, design, and IP files for a Xilinx design from scratch.
 
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