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Differences between front end design for ASIC and FPGA

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sun_ray

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If one works into ASIC design in front end. How long roughly will take for him/her to work in FPGA design for front end? What kind of changes will be there between front end design for FPGA and ASIC?
 

FPGA and ASIC design

What kind of more experience one engineer gets when he/she works in RTL, Synthesis, PAR in FPGA design compared to RTL, RTL Synthesis in ASIC design? For FPGA design the engineer will have to deal with FPGA board that has processors and other components?


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Re: FPGA and ASIC design

In my opinion about 6 - 10 months, in which an engineer is involved in all the stages (IP generation using he FPGA sw., some custom logic development, complete integration of all the IPs/logic blocks, simulation/fn-verification, synthesis, PnR, bit file generation and programming the FPGA) of a design implementation on FPGA.
 
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