Sunayana Chakradhar
Member level 5
Hello,
I am currently doing a pre RTL pin planning for my Zynq 7020 FPGA. I have a very basic question. I have few interfaces on the PS and the AXI EMC v3.0 ip core on the PL EMIO. Can i do the pin planning for this IP core before synthesizing itself?
I am currently doing a pre RTL pin planning for my Zynq 7020 FPGA. I have a very basic question. I have few interfaces on the PS and the AXI EMC v3.0 ip core on the PL EMIO. Can i do the pin planning for this IP core before synthesizing itself?
