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[SOLVED] IP core to interface parallel asynchronous SRAM with zynq 7020

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Sunayana Chakradhar

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Hello all,

I want to interface a parallel asynchronous SRAM with my Zynq 7020 FPGA. I just want to know which are all the feasible IPs that can be used to integrate these two modules?
 

Will MIG IP be sufficient? Don't I need a AXI IP to interface the PL to the PS? Please give me the entire list of IPs needed for my purpose.
 

Sunayana Chakradhar said:
Will MIG IP be sufficient? Don't I need a AXI IP to interface the PL to the PS?
Click to expand...

Here's a thought, why don't you do some work and
- Figure out what you are trying to accomplish
- Figure out what you think you need
- Go look for what you need, here is a link that will help. It is better than simply Googling https://lmgtfy.com/

Once you've gone through the above, report back on each point and then maybe you'll be able to ask a pertinent question in this forum. Until then your postings come across as someone who is simply too lazy.

Sunayana Chakradhar said:
Please give me the entire list of IPs needed for my purpose.
Click to expand...
Since you seem to have no stated purpose, no IP is required.

Kevin
 

I think there are SRAM controller IPs provided by Xilinx. Assuming you have the proper license, a controller memory IP can be generated which might have various interfaces to interact with the outside world.
e.g. The DDR3 SDRAM controller IP core can be generated with can either have an AXI4 interface or User Interface (UI) or the Native Interface.

You just have to make a self-study as to which interface suits your environment the best and then generate the IP accordingly.

Dear Mr. O.P. please play around with whatever Xilinx s/w you are having and read some docs using the "DocNav". Most of your answers will be there. Members here cannot search out or suggest IPs to you since they are are ignorant about your design environment.
 

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