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[moved] Sending 32 bit counter has four 8bit through UART

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Shruthi LS

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HI,
I want to send the 32bit counter through the UART which is of 8-bit in VHDL ...Now I am done with the 8bit counter..but I am finding difficult to send the 32bit counter and receive as a four 8bit packets..could anyone please help me...code is attached..

Code VHDL - [expand]
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library IEEE;
       
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
       
entity counter_8 is
    port(PCLK           : in  std_logic; --  APB Clock 
         CLK_5KHZ       : in  std_logic;   -- slow clock for counter
         PRESETn        : in  std_logic;         
         WEN            : out std_logic;  -- Write enable to APAB fabric interface Register
         INTR           : out std_logic;  -- interrupt to the processor when data is ready ( pulse)
         Q              : out std_logic_vector(7 downto 0)   --- Data to be stored in the FIB Register
        );
end counter_8;
-------------------------------------------------      
architecture archi of counter_8 is 
 
signal counter,ldata,markr_data : std_logic_vector(7 downto 0) ;
signal dataen_counter,markr_counter : std_logic_vector(3 downto 0) ;
signal WEN_sig, WEN_sig0,WEN_sig1 : std_logic;
signal INTR_sig0, INTR_sig1       : std_logic;
signal dataen,dataen_count_en,WEN_temp0,WEN_temp1,WEN_temp2,WEN_temp3 : std_logic;
signal en_data_ctr,en_markr_counter:std_logic;
--signal count : integer :=1;
 
begin
---------------------------------------------------
-----------------------------------------------
-------------------------------------------------
dataen_ctr_process :  process (PRESETn,PCLK)
variable last_state : std_logic := '0';    
begin
 if(PRESETn='0') then
   dataen_counter  <= (others => '0');
 elsif(PCLK'event and PCLK='1') then
   if(dataen_count_en  = '0') then
    dataen_counter  <= (others => '0');
   else    
    dataen_counter <= dataen_counter + 1;
   end if;
 end if;  
end process dataen_ctr_process  ;
---------------------------------------------
---------------------------------------------
marker_data_en_process :  process(PRESETn,PCLK)
variable last_state : std_logic := '0';    
begin
 if(PRESETn='0') then
   dataen  <= '0';    
   dataen_count_en <= '0';
   en_markr_counter <= '0';
 elsif(PCLK'event and PCLK='1') then
  if(last_state = '0' and CLK_5KHZ = '1') then
   dataen <= '1';
   dataen_count_en <= '1';
   en_markr_counter <= '1';
  else
   null;
  end if;
  if(dataen_counter = 1) then
   dataen <= '0' ;
   dataen_count_en <= '0';
  else 
   null;
  end if;
  if(en_data_ctr = '1') then
   en_markr_counter <= '0';
  else
   null;
  end if;
  last_state := CLK_5KHZ;
 end if;
end process marker_data_en_process  ;
-----------------------------------------
-----------------------------------------
header_data_process : process(PRESETn,CLK_5KHZ)
begin
 if(PRESETn='0') then
  markr_data <= x"23";  --23 is for # in  ASCII
  markr_counter <= (others => '0');
  en_data_ctr <= '0';
  ldata <= x"23";--(others => '0');
 elsif(CLK_5KHZ'event and CLK_5KHZ='1') then 
  if(en_markr_counter = '1') then
   markr_counter <= markr_counter + 1;  
   if(markr_counter >= 0 and markr_counter < 3) then
--   if(markr_counter < 3) then -- Has one extra # sent out seen in Simulation
--   if(markr_counter < 2) then -- To reduce the extra 5th #
    ldata <= markr_data;
   end if;
   if(markr_counter = 3) then
    en_data_ctr <= '1';
    markr_counter <=(others => '0');
   else
    null;
   end if;
  end if;
  if(en_data_ctr = '1') then
    ldata <= counter;
   --else
    --ldata <= ldata;
  end if;
 end if;
end process header_data_process ;
----------------------------------------------
----------------------------------------------
data_ctr_process :  process(PRESETn,CLK_5KHZ)
variable last_state : std_logic := '0';    
begin
 if(PRESETn='0') then
   counter <= (others => '0');
 elsif(CLK_5KHZ'event and CLK_5KHZ='1') then   
   if(en_data_ctr = '1') then
    counter <= counter + 1;  
   else
    counter <= counter;     
   end if;
  end if;
end process data_ctr_process;
---------------------------------------------------
--- generate the WEN of one clock cycle of PCLK for writing into the FIB register
---  dataen is pasees through a 2 level shift register with PCLK clock  and the generate a pulse 
---- in the output 
----------------------------------------------
wen2_process : process(PRESETn,PCLK)
variable last_state : std_logic := '0';
begin
 if (PRESETn='0') then
   WEN_sig0  <= '0';  
   WEN_sig1  <= '0';   
 elsif(PCLK'event and PCLK='1') then 
   WEN_sig0  <= dataen;
   WEN_sig1  <= WEN_sig0;     
 end if;    
end process wen2_process;
-------------------------------------------------
 
WEN_sig  <=  '1' when ( WEN_sig0 ='1' and WEN_sig1 ='0')  else '0';
 
----------------------------------------------
WEN_reg_process : process(PRESETn,PCLK)
begin
 if (PRESETn='0') then
   WEN_temp0  <= '0';  
   WEN_temp1  <= '0';  
   WEN_temp2  <= '0';  
   WEN_temp3  <= '0';  
 elsif(PCLK'event and PCLK='0') then 
   WEN_temp0  <= WEN_sig;  
   WEN_temp1  <= WEN_temp0;  
   WEN_temp2  <= WEN_temp1;  
   WEN_temp3  <= WEN_temp2; --    WEN_temp  <= WEN_sig;  
 end if;    
end process WEN_reg_process;
-------------------------------------------------
---  generate the Interrupt similar way as WEN
---  INTR should be generated after few clock cycle of WEN for a period one one or two PCLK clock cycle
--
----------------------------------------------
intr_process : process(PRESETn,PCLK)
begin
 if (PRESETn='0') then
   INTR_sig0  <= '0';  
   INTR_sig1  <= '0';   
 elsif(PCLK'event and PCLK='1') then 
   INTR_sig0  <= WEN_sig;
   INTR_sig1  <= INTR_sig0;     
 end if;    
end process intr_process;
-------------------------------------------------  
------------------- For the HW
WEN <= WEN_temp0;
INTR   <= INTR_sig0 xor INTR_sig1;   --- INTR signal is generated of two clock width.
Q      <= ldata;
 
end archi;
---------------------------------------------
 
Last edited by a moderator:

Re: Sending 32 bit counter has four 8bit through UART

* Your 'elseif' lines cause odd changes in text color. This implies errors in syntax.

* To make your code more legible, put a space before and after keywords.
 

Re: Sending 32 bit counter has four 8bit through UART

Hi,

First you should decide what baud rate and what UART setup you want to use. Often 8 1 is used.

With 8 1 you need to transmit 10 bits per byte:
* one start bit
* eight data bits
* one stop bit.

For transmitting 4 bytes, you should consider how you want to achieve a frame sync.

Best is to send one or multiple bytes with known value, so the receiver can recognise this pattern as sync.

Klaus
 

Re: Sending 32 bit counter has four 8bit through UART

The code in post #1 isn't related to UART, just sending 8-bit words. It's neither implementing a 32-bit counter.

Apparently you copied a third parties code that is loosely related to the thread topic, but doesn't actually help to solve it.

Writing a programmable logic design starts with a specification:
- input and output signals
- expected waveforms
- function
 

Re: Sending 32 bit counter has four 8bit through UART

Using CLK_5KHz as both a clock and as an input to the PCLK domain is a bad design practice. Also generating a signal in the CLK_5KHz domain and using it in the PCLK domain is also a bad practice. You need to learn synchronous design techniques, and I'm not going to bother with a tutorial there are more than enough of them online already...I advise you go read a few of them.

- - - Updated - - -

FvM, I think the OP posted the 8-bit counter code because they don't know how to convert it to 32-bit and then send it as 8-bit chunks over a UART. It's also probably a given with the "structure", or lack thereof, of the code, that the this wasn't designed up front but was instead designed by typing until you have something that toggles signals sort of the way you want.
 

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