[SOLVED] timing constraints in zynq 7020

Hello,

I am designing a product which interfaces an IMU, a flash, a DDR DRAM, 2 GSM modules from SIMCOM and a WIFI module from texas instruments to the zynq ZC7020 SOC.
I have looked into the data sheet of zynq 7020 ds 187. It gives timing specifications for DDR3 DRAM, QSPI flash, I2C interface etc. Also I have looked into the individual data sheets of these modules. It gives a set of timing constraints too. I am a little confused whether I should be considering the timing constraints given by the module data sheets or should i consider the timing parameters given in ds 187?

Also if there is any document to list out all the timing constraints supported on zynq, please list it below.

Thanks,
Sunayana

None of the documents you are referring to are timing constraints, they are the published timing numbers you are required to meet if you want your designs to work.

Timing constraints are what you give the tools to know what frequency you are clocking things at or what your external setup and hold time is of the logic outside the FPGA. The tools then attempt to met the published timing numbers in the device based on the constraints you provided.

I think you need to read UG945 (Vivado Design Suite Tutorial: Using Constraints) and UG903 (Vivado Deisgn Suite User Guide: Using Constraints).

Thanks a lot for your reply. I just have another question. I read on the internet that " If the uC has a I²C module then you just use it. The hardware will handle all timing issues". I just want to know when exactly timing constraints need to be written? Is it just for the soft external interfaces? Not the hardened ones? Also don't I have to define the timing constraints for the internal FPGA logic depending on the functionality I implement? That would of course be treated as a total delay of the logic block which i create.

ZYNQ is SoC (system on chip). Aside PL (FPGA fabric) there is also uController (CPU and some peripherals). Among those uController peripherals there are 2x I2C (master or slave) controllers ready to use. You don't need to do any FPGA time constraint for uController peripherals, you just connect their pins via MIO or EMIO to outside chips. If you use EMIO then you need to define pins in xdc file. Other story is if you want to implement your own I2C controller in FPGA fabric (this means writing HDL code or pick one e.g. from open cores), then you must do proper timing constrain based on scl clock rate.
Another point to keep in mind is that there will be some SW that will use this I2C controllers. Xilinx has written Linux device drivers for ZYNQ uController I2C (their set of registers and functionality). To connect them (device driver with uController I2C) you just need to define them in device tree. The benefit of device drivers is that they standardize interface to user SW (e.g. open ,close, read, write, ioctl file interface) and a lot of SW is already written. If you implement you own I2C controller (your set of registers and functionality) than SW interfacing to them is your job.