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XPower Analyzer, dynamic power

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QMA

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Dear all
what is Xpower analyzer? What is SAIF file? What is dynamic power? what is the role of dynamic power and what are the factors involved in dynamic power change?

In Xilinx if I run the simulation for longer time duration I get a smaller value of dynamic power
 

Dear all
what is Xpower analyzer? What is SAIF file? What is dynamic power? what is the role of dynamic power and what are the factors involved in dynamic power change?

In Xilinx if I run the simulation for longer time duration I get a smaller value of dynamic power

There is VCD (Value Change Dump) and SAIF (Switching Activity Interchange Format). Either file contains information on the nets switching in a simulation run. That is used to calculate the power due to switching activity throughout the design giving you a more accurate dynamic (switching) power number. Though the power number is dependent on the quality of the simulation testcase run on the design.

From what you've stated it seems you testcase is doing something at the start of simulation and then goes quiescent.
 
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    QMA

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at the start i finished simulation after 120 time slots. it gave me a value 0.058 dynamic power. then i increased simulation time and finished it after 1020 time slots. it dropped down to 0.018 dynamic power. i am not getting it.
 

at the start i finished simulation after 120 time slots. it gave me a value 0.058 dynamic power. then i increased simulation time and finished it after 1020 time slots. it dropped down to 0.018 dynamic power. i am not getting it.

This doesn't give any information that can't be gleaned from your first post.

What does your simulation do?

Suppose you have a design with a 7-bit counter and you run the counter till it saturates and then the counter stops. for the first 128 clock cycles you will have an average power number that represents the activity of the circuit while the counter is counting. If you run the same simulation for 1024 cycles you will end up with the power number representing the counter counting for 128 clock cycles and then no toggling (other than the clock) of any FFs for 896 clock cycles. Of course the average dynamic power in this case will be lower.

As you haven't described the simulation testcase nor the logic in the design, there is nothing anyone can answer for your specific case. Unless you've done the VCD/SAIF importing incorrectly your answer is probably correct you're just not giving it good simulation data. Besides numbers as low as you have means the numbers are probably going to be inaccurate anyway, as they are significantly lower than the static power (in the noise). Just the difference between max and min static will easily be 10-20 times those values.
 

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