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[SOLVED] Small fast part for tiny design

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business_kid

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I am currently limited due to a stroke,. so apologies for misspellings.

I am trying to start on 3 uncomplicated projects, and initially need a CPLD (probably) with
  • 200 Mhz
  • Less than 2 dozen I/O
  • Connect ideally to USB
  • Not going obsolete

Any ideas? I picked an ispMach4032, but Lattice Diamond-3.6 does not seem to cater for it. Do I need another software package? I also have Altera Quartus-15.1, & Anadigm Designer-2.8.0.2 installed in a vm (m$ Vista) , with Xilinx software also on an older box. My pc runs Slackware Linux.
 

You don't say what this device needs to do. Yes, it's got a small number of I/O, but you don't say whether it needs to blink a light or provide automatic steering for a car. And what do you mean "connect ideally to USB"? Do you mean you need to implement a USB stack? More information is needed to provide an intelligent answer.
 

You don't say what this device needs to do. Yes, it's got a small number of I/O, but you don't say whether it needs to blink a light or provide automatic steering for a car. And what do you mean "connect ideally to USB"? Do you mean you need to implement a USB stack? More information is needed to provide an intelligent answer.

It's got a circuit to generate & discriminate FM/FSK using period measurement, and minor glue logic (H-bridge driver, switches read into logic, etc.). I haven't gotten around to implementing usb, or even thought about it. Early stages yet. If I could buy some IP, that would save effort. USB-2.0 Would be plenty, as speeds are slow.
 

USB-2.0 Would be plenty, as speeds are slow.
Implementing any USB interface will take up far more resources than are available in a CPLD. Implementing USB 2 would likely involve adding a separate USB PHY to the board. You would be better off simply purchasing a separate USB <--> Serial UART (or SPI) chip like an FTDI FT232 and then implementing UART or SPI functionality in the CPLD to give you the communications interface.

Kevin Jennings
 

That's great, thanks. Actually, usb-1.0 is enough, as data speeds are necessarily slow. I will follow that suggestion up.
 

I agree with K-J. You don't want to start trying to implement USB in an FPGA.
 

Well it could be done in an FPGA, but a CPLD is out of the question, there is no way a USB could fit in your typical "cheap" CPLD.

In fact most big CPLDs are more expensive than some of the smaller FPGAs from Lattice and Microsemi.
 

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