VHDL error "Cannot read output :" port map error?

DNA5511 · Dec 13, 2015

Hi, so i did this program for a vending machine, the machine works fine, but i get this error, and i cant find whats wrong, this project is duw tomorrow , can some help me plz.
The errors i got:

#Error: ELAB1_0008: reu.vhd : (369, 15): Cannot read output : "Sie1".
# Error: ELAB1_0008: reu.vhd : (370, 16): Cannot read output : "Sie2".
# Error: ELAB1_0008: reu.vhd : (371, 16): Cannot read output : "Sie3".
# Error: ELAB1_0008: reu.vhd : (372, 16): Cannot read output : "Sie4".

The top level of the design:

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity cafe_pf is
    Port (
    inicio: in std_logic;
    rst: in std_logic;
        ck: in std_logic;
        Unp: in std_logic;
        DoP: in std_logic;
        Ci5: in std_logic;
        DiP: in std_logic;
        Sie1: out std_logic_vector(3 downto 0); 
        Sie2: out std_logic_vector(3 downto 0);
        Sie3: out std_logic_vector(3 downto 0)  ;
        Sie4: out std_logic_vector(3 downto 0)
        );
end cafe_pf;
 
architecture behavioral of cafe_pf is
 
type nombres_estados is (Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18);
signal estado: nombres_estados;
signal entrada_aux: std_logic_vector (3 downto 0);
 
component clk200Hz 
Port (
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC
);
end component;
 
component conta1  port(
    x : std_logic;
    clk: in std_logic;
    rst : std_logic;
    y: out std_logic);
end     component;              
 
 
 
component Seg7 
port(
x : in std_logic_vector(3 downto 0);
display : out std_logic_vector(6 downto 0)
);
end   component;
     signal ck2: std_logic;  
     signal Unp1: std_logic;   
     signal DoP2: std_logic;    
     signal Ci52: std_logic;
     signal DiP2: std_logic;  
     signal Sie11: std_logic_vector(0 to 6);
     signal Sie21: std_logic_vector(0 to 6);
     signal Sie31: std_logic_vector(0 to 6);
     signal Sie41: std_logic_vector(0 to 6);  
     signal Sie1_i: std_logic_vector(3 downto 0); 
     signal Sie1_i1: std_logic_vector(3 downto 0);
     signal Sie1_i2: std_logic_vector(3 downto 0);
     signal Sie1_i3: std_logic_vector(3 downto 0);
 
begin           
    cl: clk200hz port map(ck,rst,ck2);
    
     pulso_unpeso: conta1 port map(Unp,ck2,rst,Unp1)       ;
     pulso_dospesos: conta1 port map(DoP,ck,rst,DoP2)   ;
     pulso_cincopesos: conta1 port map(Ci5,ck,rst,Ci52) ;
     pulso_Diezpesos: conta1 port map(Dip,ck,rst,DiP2)  ;
    
    
    
entrada_aux<=DiP2&Ci52&DoP2&Unp1;
 
process(inicio, ck2)
begin   
    if rst='1' and ck2'event then 
        estado<=Q0;
    end if;
    
if inicio='1' then
    estado<=Q0;
elsif ck2='1' and ck2'event then
    case estado is
        when Q0 =>
            case entrada_aux is
                when "0000" => estado<=Q0;
                when "0001" => estado<=Q1;
                when "0010" => estado<=Q2;
                when "0100" => estado<=Q5;
                when "1000" => estado<=Q10;
                when others => estado<=Q0;
            end case;
 
        when Q1 =>
            case entrada_aux is
                when "0000" => estado<=Q1;
                when "0001" => estado<=Q2;
                when "0010" => estado<=Q3;
                when "0100" => estado<=Q6;
                when "1000" => estado<=Q11;
                when others => estado<=Q0;
            end case;
        when Q2 =>
            case entrada_aux is
                when "0000" => estado<=Q2;
                when "0001" => estado<=Q3;
                when "0010" => estado<=Q4;
                when "0101" => estado<=Q7;
                when "1010" => estado<=Q12;
                when others => estado<=Q0;
            end case;
        when Q3 =>
            case entrada_aux is
                when "0000" => estado<=Q3;
                when "0001" => estado<=Q4;
                when "0010" => estado<=Q5;
                when "0101" => estado<=Q8;
                when "1010" => estado<=Q13;
                when others => estado<=Q0;
            end case;
        when Q4 =>
            case entrada_aux is
                when "0000" => estado<=Q4;
                when "0001" => estado<=Q5;
                when "0010" => estado<=Q6;
                when "0100" => estado<=Q9;
                when "1000" => estado<=Q14;
                when others => estado<=Q0;
            end case;
        when Q5 =>
            case entrada_aux is
                when "0000" => estado<=Q5;
                when "0001" => estado<=Q6;
                when "0010" => estado<=Q7;
                when "0100" => estado<=Q10;
                when "1000" => estado<=Q15;
                when others => estado<=Q0;
            end case;
        when Q6 =>
            case entrada_aux is
                when "0000" => estado<=Q6;
                when "0001" => estado<=Q7;
                when "0010" => estado<=Q8;
                when "0100" => estado<=Q11;
                when "1000" => estado<=Q16;
                when others => estado<=Q0;
            end case;
        when Q7 =>
            case entrada_aux is
                when "0000" => estado<=Q7;
                when "0001" => estado<=Q8;
                when "0010" => estado<=Q9;
                when "0100" => estado<=Q12;
                when "1000" => estado<=Q17;
                when others => estado<=Q0;
            end case;
        when Q8 =>
            case entrada_aux is
                when "0000" => estado<=Q8;
                when "0001" => estado<=Q9;
                when "0010" => estado<=Q10;
                when "0100" => estado<=Q13;
                when "1000" => estado<=Q18;
                when others => estado<=Q0;
            end case;
        when Q9 =>
            case entrada_aux is
                when "0000" => estado<=Q0;
                when "0001" => estado<=Q1;
                when "0010" => estado<=Q2;
                when "0100" => estado<=Q5;
                when "1000" => estado<=Q10;
                when others => estado<=Q0;
            end case;
        when Q10 =>
            case entrada_aux is
                when "0000" => estado<=Q0;
                when "0001" => estado<=Q1;
                when "0010" => estado<=Q2;
                when "0100" => estado<=Q5;
                when "1000" => estado<=Q10;
                when others => estado<=Q0;
            end case;
        when Q11 =>
            case entrada_aux is
                when "0000" => estado<=Q0;
                when "0001" => estado<=Q1;
                when "0010" => estado<=Q2;
                when "0100" => estado<=Q5;
                when "1000" => estado<=Q10;
                when others => estado<=Q0;
            end case;
        when Q12 =>
            case entrada_aux is
                when "0000" => estado<=Q0;
                when "0001" => estado<=Q1;
                when "0010" => estado<=Q2;
                when "0100" => estado<=Q5;
                when "1000" => estado<=Q10;
                when others => estado<=Q0;
            end case;
        when Q13 =>
            case entrada_aux is
                when "0000" => estado<=Q0;
                when "0001" => estado<=Q1;
                when "0010" => estado<=Q2;
                when "0100" => estado<=Q5;
                when "1000" => estado<=Q10;
                when others => estado<=Q0;
            end case;
        when Q14 =>
            case entrada_aux is
                when "0000" => estado<=Q0;
                when "0001" => estado<=Q1;
                when "0010" => estado<=Q2;
                when "0100" => estado<=Q5;
                when "1000" => estado<=Q10;
                when others => estado<=Q0;
            end case;
 
        when Q15 =>
            case entrada_aux is
                when "0000" => estado<=Q0;
                when "0001" => estado<=Q1;
                when "0010" => estado<=Q2;
                when "0100" => estado<=Q5;
                when "1000" => estado<=Q10;
                when others => estado<=Q0;
            end case;
        when Q16 =>
            case entrada_aux is
                when "0000" => estado<=Q0;
                when "0001" => estado<=Q1;
                when "0010" => estado<=Q2;
                when "0100" => estado<=Q5;
                when "1000" => estado<=Q10;
                when others => estado<=Q0;
            end case;
        when Q17 =>
            case entrada_aux is
                when "0000" => estado<=Q0;
                when "0001" => estado<=Q1;
                when "0010" => estado<=Q2;
                when "0100" => estado<=Q5;
                when "1000" => estado<=Q10;
                when others => estado<=Q0;
            end case;
        when Q18 =>
            case entrada_aux is
                when "0000" => estado<=Q0;
                when "0001" => estado<=Q1;
                when "0010" => estado<=Q2;
                when "0100" => estado<=Q5;
                when "1000" => estado<=Q10;
                when others => estado<=Q0;
            end case;
        when others => estado<=Q0;
    end case;
end if;
end process;
 
process(estado)
begin
case estado is
    when Q0 =>
        Sie1<="0000";
        Sie2<="0000";
        Sie3<="0000"; 
        Sie4<="0000";
        
        
    when Q1 =>
        Sie1<="0000";
        Sie2<="0001";
        Sie3<="0000";
        Sie4<="0000";   
    when Q2 =>
        Sie1<="0000";
        Sie2<="0010";
        Sie3<="0000";
        Sie4<="0000";   
    when Q3 =>
        Sie1<="0000";
        Sie2<="0011";
        Sie3<="0000";
        Sie4<="0000";   
    when Q4 =>
        Sie1<="0000";
        Sie2<="0100";
        Sie3<="0000";
        Sie4<="0000";   
    when Q5 =>
        Sie1<="0000";
        Sie2<="0101";
        Sie3<="0000";
        Sie4<="0000";   
    when Q6 =>
        Sie1<="0000";
        Sie2<="0110";
        Sie3<="0000"; 
        Sie4<="0000";   
    when Q7 =>
        Sie1<="0000";
        Sie2<="0111";
        Sie3<="0000";
        Sie4<="0000";   
    when Q8 =>
        Sie1<="0000";
        Sie2<="1000";
        Sie3<="0000";
        Sie4<="0000";   
    when Q9 =>
        Sie1<="0000";
        Sie2<="1001";
        Sie3<="1111";
        Sie4<="0000";   
    when Q10 =>
        Sie1<="0001";
        Sie2<="0000";
        Sie3<="1111";
        Sie4<="0001";   
    when Q11 =>
        Sie1<="0001";
        Sie2<="0001";
        Sie3<="1111";
        Sie4<="0010";   
    when Q12 =>
        Sie1<="0001" ;
        Sie2<="0010";
        Sie3<="1111";
        Sie4<="0011";   
    when Q13 =>
        Sie1<="0001" ;
        Sie2<="0011";
        Sie3<="1111";
        Sie4<="0100";   
    when Q14 =>
        Sie1<="0001";
        Sie2<="0100";
        Sie3<="1111";
        Sie4<="0101";   
    when Q15 =>
        Sie1<="0001";            
        Sie2<="0101";
        Sie3<="1111";
        Sie4<="0110";   
    when Q16 =>
        Sie1<="0001";
        Sie2<="0110";
        Sie3<="0001";
        Sie4<="0111";   
    when Q17 =>
        Sie1<="0001";
        Sie2<="0111";
        Sie3<="1111";
        Sie4<="1000";   
    when Q18 =>
        Sie1<="0001";
        Sie2<="1000";
        Sie3<="1111";
        Sie4<="1001";    
        
end case;   
                 
end process; 
    Sie1_i <= Sie1;     -----Error here
    Sie1_i1 <= Sie2;    -----Error here
    Sie1_i2 <= Sie3;    -----Error here
    Sie1_i3 <= Sie4;    -----Error here
     
     display_1: seg7 port map(Sie1_i, Sie11);
     display_2: seg7 port map(Sie1_i1,Sie21);
     display_3: seg7 port map(Sie1_i2,Sie31);
     display_4: seg7 port map(Sie1_i3,Sie41);
 
end behavioral;

i cant find , or understand whats wrong

andre_luis · Dec 13, 2015

I'm not sure if this is allowed, or not, but I noticed you are attempting to store values from variables defined as out to variables defined as signal.

FvM · Dec 13, 2015

You can either enable VHDL-2008 syntax, if supported by your compiler, or should respect the pre-2008 syntax rules.

It seems to me that the Sie_i etc. signals have been introduced to overcome the restriction of out mode port parameters, but unfortunately not used as required.

Instead you would write to and read from the Sie_i signals inside the component and copy them once to the port signals.

DNA5511 · Dec 14, 2015

i change it to 2008 syntax, and it worked.

So..............
It should work now, the right way, or whats the difference between 2002 and 2008, i mean it should work the way i programmed it, right?
Ill try it tomorrow on the fpga, and see what happens

FvM · Dec 14, 2015

It's no actual design error, it's a restriction of the (pre-2008) VHDL specification, saying the out port signals can't be read. You surely find it discussed in your VHLD textbook or tutorial. In terms of hardware design, there's no problem involved with reading an out port.

Another way to overcome it is to declare the respective port signals as "buffer" instead of "out". In some very strict VHDL implementations, buffer ports must be exclusively connected to buffer ports in the upper hierarchies, but most compilers accept a connection to out as well.

DNA5511 · Dec 14, 2015

FvM said:
It's no actual design error, it's a restriction of the (pre-2008) VHDL specification, saying the out port signals can't be read. You surely find it discussed in your VHLD textbook or tutorial. In terms of hardware design, there's no problem involved with reading an out port.

Another way to overcome it is to declare the respective port signals as "buffer" instead of "out". In some very strict VHDL implementations, buffer ports must be exclusively connected to buffer ports in the upper hierarchies, but most compilers accept a connection to out as well.

i have never used buffer before, i try it, and it didnt work, can you show me an example, in my code plz, ty by the way.

I also change the compiler to 2008 and it work, but when i try it on quartus it shows the same error, even when i changed the compiler of quartus to 2008............ im ding here

TrickyDicky · Dec 14, 2015

Unfortunately Quartus is now starting to lag. While it has supported some VHDL 2008 features for some time, reading out ports is not one of them.

You will have to either use a buffer, or use a temporary internal signal (as it the usual recommended way)
For buffer, just replace the word "out" in the port declaration with buffer:

output : buffer std_logic;

std_match · Dec 14, 2015

Please use the "safe" solution, an intermediate signal that can be read in the process.
The intermediate signal is assigned to the output.
This will work with all tools and any VHDL version.

Avoid using "buffer". It will cause a lot of trouble when used with tools that strictly follows the VHDL standard. The problem appears when entities are connected to each other in a hierarchy.

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VHDL error "Cannot read output :" port map error?

DNA5511

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andre_luis

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FvM

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DNA5511

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FvM

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DNA5511

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DNA5511

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DNA5511

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