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[SOLVED] Basic spi timing issues help

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harry998

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Hi guys ive been playin around with altera fpga's for a while and managed a few basic projects but im struggling with this one and none of the books and tutorials ive got seem to help (i think it might be a timing issues)

The code is for a very basic spi master that esseential just transmits a 1 byte instruction in spi protocol.
The count register keeps track of how many spi clocks have gone past and should output a high bit on clock 7 and 8 at the minute i get a high clock output at (approx because i dont have my scope with me) the 15th clock falling edge.
* note its a repeating signal every 15 ish clocks not just a one shot

Is this a timing issue or am i doing something obviously silly? :-S


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module spimaster (clk, cs, spiclk, datain, dataoutpin);
 
input clk, datain;
output   cs, spiclk, doutp;
reg spireg;
reg  [9:0] tick;
reg  [4:0] count;
reg [4:0] moso;
reg [9:0] mosi;
reg [9:0] data;
reg [0:0] dout;
 
 
////////////////////////////////////////////////////////// clk ///////////
initial 
begin
moso [4:0] = 24;
end
 
 
always@ (negedge clk)                                //generate spi clk
begin
tick <= tick + 1;
if (tick == 0)
spireg = ~spireg;
end
 
always@ (negedge spireg)                                        // track number of clock cycles
begin
count = count + 1;
 
end
 
 
 always@ (negedge clk)
 
if (count == 7)
dout = 1;
else if (count == 8)
dout = 1;
else
dout = 0;
 
assign dataout = dout;
assign cs = !(count <= 25);
assign spiclk = spireg;
 
endmodule
 
Last edited by a moderator:

This is probably a timing issue from poor design practice. Generating a clock with logic can be prone to timing issues. I would move the counter in to the clock domain and your problems may go away
 

ok thank you il go and review clock domains again and try and come up with something better
 

I didn't look at your code earlier, but now that I have you've got lots of typo problems and you've got to learn Verilog 2001 instead of using antiquated coding of the module ports that can result in more typing and errors like you have.

e.g.

module spimaster (clk, cs, spiclk, datain, dataoutpin);

is not the same set of signals...
input clk, datain;
output cs, spiclk, doutp;

dataoutpin is not going to be connected to doutp.

You are also not using the conventional SPI signal names...
SCLK, CS_N, MOSI, and MISO for the ports of the module. You also named MISO as moso (master out slave out!)

You are missing any kind of shifting of the MOSI and MISO to the output and input respectively.

I'm not even going to attempt to analyze any more of the code as this isn't even close to functional.
 

Its all working now :) it was as suggested timing issues, ive generated a the clock with a pll and everything is behaving as should.

Forgive the typos the actual code was enormous mess from days of frustration hence port labelled in various different ways. The shifting etc was removed to simplify the code and try and find the problem, the high output on count = 7 and count = 8 is all i needed to tell the slave to respond which it is now thank god :-D

Fpga's are an interest / hobby for me so when i do get spare time i have to learn at a fast pace to get anything done and sometimes its easier to has things together and learn by experience than try and get everything perfect first time.

Thank you for your time and your help anyway, i try to solve my own issues and get there most of the time but i would never have found the timing problem!
 

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