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how to create an acknowlegdement signal in vhdl?

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prashanthi999

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hello guys, i have "xr" as my input signal and output signal "zr" , "xr" receives the input, after a delay of n clock cycles it generates a "zr" output signal , so when ever i get my "zr" i want to have acknowledgement for it, how to create those acknowlegment signals in vhdl.
 

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