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I have some questions in the verilog code of 8051 ALU module

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helimpopo

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Code:
   TC_int  = TC | 1'b0;
   LEQ_int = LEQ | 1'b0;

TC determines whether the number is signed or unsigned, so what does TC|1'b0 mean? Is there any difference between signal TC and TC_int? TC is a one bit signal.

Another question.

I find the verilog code of ALU very interesting. The coder wrote the CMP like:

Code:
        if ( TC === 1'b0 ) begin  // unsigned numbers
          result = 0;
          for (i = 0; i <= sign; i = i + 1) begin
              a_is_0 = A[i] === 1'b0;
              b_is_1 = B[i] === 1'b1;
              result = (a_is_0 & b_is_1) |
                        (a_is_0 & result) |
                        (b_is_1 & result);
          end // loop

What are the advantages by writing a comparator like this? If I were the writer, I could only come up with the '<' and '>' symbols. There may be some considerations in systhesized circuits, but how can I know these tiny differences?
 

Code:
   TC_int  = TC | 1'b0;
   LEQ_int = LEQ | 1'b0;

TC determines whether the number is signed or unsigned, so what does TC|1'b0 mean? Is there any difference between signal TC and TC_int? TC is a one bit signal.
That is a bitwise OR, so TC and TC_int are the same signal. I'm assuming this code is in an always @* block.

I find the verilog code of ALU very interesting. The coder wrote the CMP like:

Code:
        if ( TC === 1'b0 ) begin  // unsigned numbers
          result = 0;
          for (i = 0; i <= sign; i = i + 1) begin
              a_is_0 = A[i] === 1'b0;
              b_is_1 = B[i] === 1'b1;
              result = (a_is_0 & b_is_1) |
                        (a_is_0 & result) |
                        (b_is_1 & result);
          end // loop

What are the advantages by writing a comparator like this? If I were the writer, I could only come up with the '<' and '>' symbols. There may be some considerations in systhesized circuits, but how can I know these tiny differences?
Oddly enough I don't recall === being synthesizable, and I can't find anything that would suggest it is in the LRM. The examples in the LRM use it for testbench type stuff. I'd love to know where you found code like this. I would never write a comparison like this, there's no good reason I can fathom why it was done this way.
 

The difference between TC and TC_int is that a 1'bz state in TC will get converted to 1'bx. It would make a difference if these signals were used in a casez() statement, but only if they could have been assigned the 1'bz value.

The comparator is written this way to reduce X pessimism by doing the comparison bit by bit. The === operator is only different from the == operator when comparing a value with an unknown in it. So in this example, it is not doing anything.
 
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