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Error:NgdBuild:924 - input pad net 'clk' is driving non-buffer primitives:

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RAVI30

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Hi,
I design protocol, but when i implementing the design using ZYBO board. i have used constraint file, but i get Error when translating the design,


Error is:
ERROR:NgdBuild:924 - input pad net 'clk' is driving non-buffer primitives:
 

Not totally clear, but you apparently need to add a buffer on your clock input. You don't give us a lot of information...
 

You have a pin that is connected to something inside the FPGA that is not an input buffer like an IBUF or IBUFG or such. Normally ports on a module/entity have the input/output buffers inserted automatically (maybe you turned off buffer insertion?).

You should post your HDL code for that port and how you use it in the code, if you want more than just conjecture.
 

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