beginner_EDA
Full Member level 4
Hi,
I would like to implement 512 point FFT on Altera Cyclone IVE FPGA using VHDL/Verilog.
What are the option available for it?
1. How complex it is to implement? how much resources(logic gates from FPGA) normally it consumes?
2. Is there any reference design for this with which one can start?
3. Is it advisable to use Altera's IP Core for this due to complexity or one can design self with some effort? If yes, is FFT IP core of Altera free or paid. in case paid, how much does it cost round about?
Regards
I would like to implement 512 point FFT on Altera Cyclone IVE FPGA using VHDL/Verilog.
What are the option available for it?
1. How complex it is to implement? how much resources(logic gates from FPGA) normally it consumes?
2. Is there any reference design for this with which one can start?
3. Is it advisable to use Altera's IP Core for this due to complexity or one can design self with some effort? If yes, is FFT IP core of Altera free or paid. in case paid, how much does it cost round about?
Regards