[SOLVED] Systematic Cyclic Encoder in VHDL

Morell said:

This is the latest version of my encoder module.
Hi

1-This is my questions :

a)Does this code works on a board (Xilinx Spartan-3)?

b)If it doesn't, What do you think the problem is?

c)How can I solve the problem and make it work (Implement on a board)?

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Does this mean you've tried it on a Spartan-3 board and it doesn't work? Or you can't get the tools to generate a bit file? Or synthesis doesn't work? What is the problem?

Morell said:

2- I simulate it and it worked (as expected!!!).

3- Attached file is going to say what the code should do.

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Well simulation only works as well as the code that is used to stimulate the design. Bad/wrong testbench will result in poor or non-existent functional coverage. You've never supplied the testbench, so can't asses how well your functional coverage verified the design.

Morell said:

4- Others things (Readability, Modularity and so on) are not important right now.
Specially if the code works on a board.

5- This module (Encoder_3v2) is a component in another module (Encode).
And right now Encode is not the major part because I didn't finished Encoder_3v2.
But I would like to know your suggestions and tips about the design of the Top module (Encode)

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Fine, but you never did address the comment I made in the reformatted code about the counter saturating and stopping...(is reset used as a load?)

I suspect some tool misunderstandings. Morell's changes didn't exactly follow all of my advice.

This is an expanding design -- the number of valid output cycles is more than the number of valid input cycles. As a result, cycle vs sample delay is important. Too much logic is based only on (valid_in = '1').

If this works, it is possible the simulator is using a previously compiled version of the RTL. It is also possible the valid_in/valid_out concepts were not understood. In all cases, you should specify how you think the interface in/out of the modules will work.


(With all of the info given, the 4,7 block codes would be lookup tables in modern FPGAs. the fancy encoders would go away as FPGA primitives allow the basic approach to work.)

I suspect some tool misunderstandings. Morell's changes didn't exactly follow all of my advice.

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Would you mind giving me your template of writing this code again, please?

It is on this thread, i think page 2?

The main point is that you cannot generate the data_out and valid_out just from valid_in. the valid_out is based on both valid_in, as well as the state of your Switch2 signal.

Hi Guys,
Thanks alot for your help,
It all Worked pretty well,